stm32l4/stm32l4x5/rcc/
ahb1enr.rs

1///Register `AHB1ENR` reader
2pub type R = crate::R<AHB1ENRrs>;
3///Register `AHB1ENR` writer
4pub type W = crate::W<AHB1ENRrs>;
5///Field `DMA1EN` reader - DMA1 clock enable
6pub type DMA1EN_R = crate::BitReader;
7///Field `DMA1EN` writer - DMA1 clock enable
8pub type DMA1EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `DMA2EN` reader - DMA2 clock enable
10pub type DMA2EN_R = crate::BitReader;
11///Field `DMA2EN` writer - DMA2 clock enable
12pub type DMA2EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `FLASHEN` reader - Flash memory interface clock enable
14pub type FLASHEN_R = crate::BitReader;
15///Field `FLASHEN` writer - Flash memory interface clock enable
16pub type FLASHEN_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `CRCEN` reader - CRC clock enable
18pub type CRCEN_R = crate::BitReader;
19///Field `CRCEN` writer - CRC clock enable
20pub type CRCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `TSCEN` reader - Touch Sensing Controller clock enable
22pub type TSCEN_R = crate::BitReader;
23///Field `TSCEN` writer - Touch Sensing Controller clock enable
24pub type TSCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    ///Bit 0 - DMA1 clock enable
27    #[inline(always)]
28    pub fn dma1en(&self) -> DMA1EN_R {
29        DMA1EN_R::new((self.bits & 1) != 0)
30    }
31    ///Bit 1 - DMA2 clock enable
32    #[inline(always)]
33    pub fn dma2en(&self) -> DMA2EN_R {
34        DMA2EN_R::new(((self.bits >> 1) & 1) != 0)
35    }
36    ///Bit 8 - Flash memory interface clock enable
37    #[inline(always)]
38    pub fn flashen(&self) -> FLASHEN_R {
39        FLASHEN_R::new(((self.bits >> 8) & 1) != 0)
40    }
41    ///Bit 12 - CRC clock enable
42    #[inline(always)]
43    pub fn crcen(&self) -> CRCEN_R {
44        CRCEN_R::new(((self.bits >> 12) & 1) != 0)
45    }
46    ///Bit 16 - Touch Sensing Controller clock enable
47    #[inline(always)]
48    pub fn tscen(&self) -> TSCEN_R {
49        TSCEN_R::new(((self.bits >> 16) & 1) != 0)
50    }
51}
52impl core::fmt::Debug for R {
53    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
54        f.debug_struct("AHB1ENR")
55            .field("tscen", &self.tscen())
56            .field("crcen", &self.crcen())
57            .field("flashen", &self.flashen())
58            .field("dma2en", &self.dma2en())
59            .field("dma1en", &self.dma1en())
60            .finish()
61    }
62}
63impl W {
64    ///Bit 0 - DMA1 clock enable
65    #[inline(always)]
66    pub fn dma1en(&mut self) -> DMA1EN_W<AHB1ENRrs> {
67        DMA1EN_W::new(self, 0)
68    }
69    ///Bit 1 - DMA2 clock enable
70    #[inline(always)]
71    pub fn dma2en(&mut self) -> DMA2EN_W<AHB1ENRrs> {
72        DMA2EN_W::new(self, 1)
73    }
74    ///Bit 8 - Flash memory interface clock enable
75    #[inline(always)]
76    pub fn flashen(&mut self) -> FLASHEN_W<AHB1ENRrs> {
77        FLASHEN_W::new(self, 8)
78    }
79    ///Bit 12 - CRC clock enable
80    #[inline(always)]
81    pub fn crcen(&mut self) -> CRCEN_W<AHB1ENRrs> {
82        CRCEN_W::new(self, 12)
83    }
84    ///Bit 16 - Touch Sensing Controller clock enable
85    #[inline(always)]
86    pub fn tscen(&mut self) -> TSCEN_W<AHB1ENRrs> {
87        TSCEN_W::new(self, 16)
88    }
89}
90/**AHB1 peripheral clock enable register
91
92You can [`read`](crate::Reg::read) this register and get [`ahb1enr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb1enr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
93
94See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#RCC:AHB1ENR)*/
95pub struct AHB1ENRrs;
96impl crate::RegisterSpec for AHB1ENRrs {
97    type Ux = u32;
98}
99///`read()` method returns [`ahb1enr::R`](R) reader structure
100impl crate::Readable for AHB1ENRrs {}
101///`write(|w| ..)` method takes [`ahb1enr::W`](W) writer structure
102impl crate::Writable for AHB1ENRrs {
103    type Safety = crate::Unsafe;
104}
105///`reset()` method sets AHB1ENR to value 0x0100
106impl crate::Resettable for AHB1ENRrs {
107    const RESET_VALUE: u32 = 0x0100;
108}
stm32l4/stm32l4x5/rcc/ahb1enr.rs

stm32l4/stm32l4x5/rcc/
ahb1enr.rs
