stm32l4/stm32l4x5/lpuart1/
icr.rs

1///Register `ICR` writer
2pub type W = crate::W<ICRrs>;
3/**Parity error clear flag
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum PECF {
9    ///1: Clears the PE flag in the ISR register
10    Clear = 1,
11}
12impl From<PECF> for bool {
13    #[inline(always)]
14    fn from(variant: PECF) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `PECF` writer - Parity error clear flag
19pub type PECF_W<'a, REG> = crate::BitWriter1C<'a, REG, PECF>;
20impl<'a, REG> PECF_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Clears the PE flag in the ISR register
25    #[inline(always)]
26    pub fn clear(self) -> &'a mut crate::W<REG> {
27        self.variant(PECF::Clear)
28    }
29}
30/**Framing error clear flag
31
32Value on reset: 0*/
33#[cfg_attr(feature = "defmt", derive(defmt::Format))]
34#[derive(Clone, Copy, Debug, PartialEq, Eq)]
35pub enum FECF {
36    ///1: Clears the FE flag in the ISR register
37    Clear = 1,
38}
39impl From<FECF> for bool {
40    #[inline(always)]
41    fn from(variant: FECF) -> Self {
42        variant as u8 != 0
43    }
44}
45///Field `FECF` writer - Framing error clear flag
46pub type FECF_W<'a, REG> = crate::BitWriter1C<'a, REG, FECF>;
47impl<'a, REG> FECF_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    ///Clears the FE flag in the ISR register
52    #[inline(always)]
53    pub fn clear(self) -> &'a mut crate::W<REG> {
54        self.variant(FECF::Clear)
55    }
56}
57/**Noise detected clear flag
58
59Value on reset: 0*/
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum NCF {
63    ///1: Clears the NF flag in the ISR register
64    Clear = 1,
65}
66impl From<NCF> for bool {
67    #[inline(always)]
68    fn from(variant: NCF) -> Self {
69        variant as u8 != 0
70    }
71}
72///Field `NCF` writer - Noise detected clear flag
73pub type NCF_W<'a, REG> = crate::BitWriter1C<'a, REG, NCF>;
74impl<'a, REG> NCF_W<'a, REG>
75where
76    REG: crate::Writable + crate::RegisterSpec,
77{
78    ///Clears the NF flag in the ISR register
79    #[inline(always)]
80    pub fn clear(self) -> &'a mut crate::W<REG> {
81        self.variant(NCF::Clear)
82    }
83}
84/**Overrun error clear flag
85
86Value on reset: 0*/
87#[cfg_attr(feature = "defmt", derive(defmt::Format))]
88#[derive(Clone, Copy, Debug, PartialEq, Eq)]
89pub enum ORECF {
90    ///1: Clears the ORE flag in the ISR register
91    Clear = 1,
92}
93impl From<ORECF> for bool {
94    #[inline(always)]
95    fn from(variant: ORECF) -> Self {
96        variant as u8 != 0
97    }
98}
99///Field `ORECF` writer - Overrun error clear flag
100pub type ORECF_W<'a, REG> = crate::BitWriter1C<'a, REG, ORECF>;
101impl<'a, REG> ORECF_W<'a, REG>
102where
103    REG: crate::Writable + crate::RegisterSpec,
104{
105    ///Clears the ORE flag in the ISR register
106    #[inline(always)]
107    pub fn clear(self) -> &'a mut crate::W<REG> {
108        self.variant(ORECF::Clear)
109    }
110}
111/**Idle line detected clear flag
112
113Value on reset: 0*/
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum IDLECF {
117    ///1: Clears the IDLE flag in the ISR register
118    Clear = 1,
119}
120impl From<IDLECF> for bool {
121    #[inline(always)]
122    fn from(variant: IDLECF) -> Self {
123        variant as u8 != 0
124    }
125}
126///Field `IDLECF` writer - Idle line detected clear flag
127pub type IDLECF_W<'a, REG> = crate::BitWriter1C<'a, REG, IDLECF>;
128impl<'a, REG> IDLECF_W<'a, REG>
129where
130    REG: crate::Writable + crate::RegisterSpec,
131{
132    ///Clears the IDLE flag in the ISR register
133    #[inline(always)]
134    pub fn clear(self) -> &'a mut crate::W<REG> {
135        self.variant(IDLECF::Clear)
136    }
137}
138/**Transmission complete clear flag
139
140Value on reset: 0*/
141#[cfg_attr(feature = "defmt", derive(defmt::Format))]
142#[derive(Clone, Copy, Debug, PartialEq, Eq)]
143pub enum TCCF {
144    ///1: Clears the TC flag in the ISR register
145    Clear = 1,
146}
147impl From<TCCF> for bool {
148    #[inline(always)]
149    fn from(variant: TCCF) -> Self {
150        variant as u8 != 0
151    }
152}
153///Field `TCCF` writer - Transmission complete clear flag
154pub type TCCF_W<'a, REG> = crate::BitWriter1C<'a, REG, TCCF>;
155impl<'a, REG> TCCF_W<'a, REG>
156where
157    REG: crate::Writable + crate::RegisterSpec,
158{
159    ///Clears the TC flag in the ISR register
160    #[inline(always)]
161    pub fn clear(self) -> &'a mut crate::W<REG> {
162        self.variant(TCCF::Clear)
163    }
164}
165/**CTS clear flag
166
167Value on reset: 0*/
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum CTSCF {
171    ///1: Clears the CTSIF flag in the ISR register
172    Clear = 1,
173}
174impl From<CTSCF> for bool {
175    #[inline(always)]
176    fn from(variant: CTSCF) -> Self {
177        variant as u8 != 0
178    }
179}
180///Field `CTSCF` writer - CTS clear flag
181pub type CTSCF_W<'a, REG> = crate::BitWriter1C<'a, REG, CTSCF>;
182impl<'a, REG> CTSCF_W<'a, REG>
183where
184    REG: crate::Writable + crate::RegisterSpec,
185{
186    ///Clears the CTSIF flag in the ISR register
187    #[inline(always)]
188    pub fn clear(self) -> &'a mut crate::W<REG> {
189        self.variant(CTSCF::Clear)
190    }
191}
192/**Character match clear flag
193
194Value on reset: 0*/
195#[cfg_attr(feature = "defmt", derive(defmt::Format))]
196#[derive(Clone, Copy, Debug, PartialEq, Eq)]
197pub enum CMCF {
198    ///1: Clears the CMF flag in the ISR register
199    Clear = 1,
200}
201impl From<CMCF> for bool {
202    #[inline(always)]
203    fn from(variant: CMCF) -> Self {
204        variant as u8 != 0
205    }
206}
207///Field `CMCF` writer - Character match clear flag
208pub type CMCF_W<'a, REG> = crate::BitWriter1C<'a, REG, CMCF>;
209impl<'a, REG> CMCF_W<'a, REG>
210where
211    REG: crate::Writable + crate::RegisterSpec,
212{
213    ///Clears the CMF flag in the ISR register
214    #[inline(always)]
215    pub fn clear(self) -> &'a mut crate::W<REG> {
216        self.variant(CMCF::Clear)
217    }
218}
219/**Wakeup from Stop mode clear flag
220
221Value on reset: 0*/
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum WUCF {
225    ///1: Clears the WUF flag in the ISR register
226    Clear = 1,
227}
228impl From<WUCF> for bool {
229    #[inline(always)]
230    fn from(variant: WUCF) -> Self {
231        variant as u8 != 0
232    }
233}
234///Field `WUCF` writer - Wakeup from Stop mode clear flag
235pub type WUCF_W<'a, REG> = crate::BitWriter1C<'a, REG, WUCF>;
236impl<'a, REG> WUCF_W<'a, REG>
237where
238    REG: crate::Writable + crate::RegisterSpec,
239{
240    ///Clears the WUF flag in the ISR register
241    #[inline(always)]
242    pub fn clear(self) -> &'a mut crate::W<REG> {
243        self.variant(WUCF::Clear)
244    }
245}
246impl core::fmt::Debug for crate::generic::Reg<ICRrs> {
247    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
248        write!(f, "(not readable)")
249    }
250}
251impl W {
252    ///Bit 0 - Parity error clear flag
253    #[inline(always)]
254    pub fn pecf(&mut self) -> PECF_W<ICRrs> {
255        PECF_W::new(self, 0)
256    }
257    ///Bit 1 - Framing error clear flag
258    #[inline(always)]
259    pub fn fecf(&mut self) -> FECF_W<ICRrs> {
260        FECF_W::new(self, 1)
261    }
262    ///Bit 2 - Noise detected clear flag
263    #[inline(always)]
264    pub fn ncf(&mut self) -> NCF_W<ICRrs> {
265        NCF_W::new(self, 2)
266    }
267    ///Bit 3 - Overrun error clear flag
268    #[inline(always)]
269    pub fn orecf(&mut self) -> ORECF_W<ICRrs> {
270        ORECF_W::new(self, 3)
271    }
272    ///Bit 4 - Idle line detected clear flag
273    #[inline(always)]
274    pub fn idlecf(&mut self) -> IDLECF_W<ICRrs> {
275        IDLECF_W::new(self, 4)
276    }
277    ///Bit 6 - Transmission complete clear flag
278    #[inline(always)]
279    pub fn tccf(&mut self) -> TCCF_W<ICRrs> {
280        TCCF_W::new(self, 6)
281    }
282    ///Bit 9 - CTS clear flag
283    #[inline(always)]
284    pub fn ctscf(&mut self) -> CTSCF_W<ICRrs> {
285        CTSCF_W::new(self, 9)
286    }
287    ///Bit 17 - Character match clear flag
288    #[inline(always)]
289    pub fn cmcf(&mut self) -> CMCF_W<ICRrs> {
290        CMCF_W::new(self, 17)
291    }
292    ///Bit 20 - Wakeup from Stop mode clear flag
293    #[inline(always)]
294    pub fn wucf(&mut self) -> WUCF_W<ICRrs> {
295        WUCF_W::new(self, 20)
296    }
297}
298/**Interrupt flag clear register
299
300You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
301
302See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#LPUART1:ICR)*/
303pub struct ICRrs;
304impl crate::RegisterSpec for ICRrs {
305    type Ux = u32;
306}
307///`write(|w| ..)` method takes [`icr::W`](W) writer structure
308impl crate::Writable for ICRrs {
309    type Safety = crate::Unsafe;
310    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0012_025f;
311}
312///`reset()` method sets ICR to value 0
313impl crate::Resettable for ICRrs {}
stm32l4/stm32l4x5/lpuart1/icr.rs

stm32l4/stm32l4x5/lpuart1/
icr.rs
