stm32l4/stm32l4x5/lpuart1/
cr3.rs

1///Register `CR3` reader
2pub type R = crate::R<CR3rs>;
3///Register `CR3` writer
4pub type W = crate::W<CR3rs>;
5/**Error interrupt enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum EIE {
11    ///0: Interrupt is inhibited
12    Disabled = 0,
13    ///1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
14    Enabled = 1,
15}
16impl From<EIE> for bool {
17    #[inline(always)]
18    fn from(variant: EIE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `EIE` reader - Error interrupt enable
23pub type EIE_R = crate::BitReader<EIE>;
24impl EIE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> EIE {
28        match self.bits {
29            false => EIE::Disabled,
30            true => EIE::Enabled,
31        }
32    }
33    ///Interrupt is inhibited
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == EIE::Disabled
37    }
38    ///An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == EIE::Enabled
42    }
43}
44///Field `EIE` writer - Error interrupt enable
45pub type EIE_W<'a, REG> = crate::BitWriter<'a, REG, EIE>;
46impl<'a, REG> EIE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Interrupt is inhibited
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(EIE::Disabled)
54    }
55    ///An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(EIE::Enabled)
59    }
60}
61/**Half-duplex selection
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum HDSEL {
67    ///0: Half duplex mode is not selected
68    NotSelected = 0,
69    ///1: Half duplex mode is selected
70    Selected = 1,
71}
72impl From<HDSEL> for bool {
73    #[inline(always)]
74    fn from(variant: HDSEL) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `HDSEL` reader - Half-duplex selection
79pub type HDSEL_R = crate::BitReader<HDSEL>;
80impl HDSEL_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> HDSEL {
84        match self.bits {
85            false => HDSEL::NotSelected,
86            true => HDSEL::Selected,
87        }
88    }
89    ///Half duplex mode is not selected
90    #[inline(always)]
91    pub fn is_not_selected(&self) -> bool {
92        *self == HDSEL::NotSelected
93    }
94    ///Half duplex mode is selected
95    #[inline(always)]
96    pub fn is_selected(&self) -> bool {
97        *self == HDSEL::Selected
98    }
99}
100///Field `HDSEL` writer - Half-duplex selection
101pub type HDSEL_W<'a, REG> = crate::BitWriter<'a, REG, HDSEL>;
102impl<'a, REG> HDSEL_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Half duplex mode is not selected
107    #[inline(always)]
108    pub fn not_selected(self) -> &'a mut crate::W<REG> {
109        self.variant(HDSEL::NotSelected)
110    }
111    ///Half duplex mode is selected
112    #[inline(always)]
113    pub fn selected(self) -> &'a mut crate::W<REG> {
114        self.variant(HDSEL::Selected)
115    }
116}
117/**DMA enable receiver
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum DMAR {
123    ///0: DMA mode is disabled for reception
124    Disabled = 0,
125    ///1: DMA mode is enabled for reception
126    Enabled = 1,
127}
128impl From<DMAR> for bool {
129    #[inline(always)]
130    fn from(variant: DMAR) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `DMAR` reader - DMA enable receiver
135pub type DMAR_R = crate::BitReader<DMAR>;
136impl DMAR_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> DMAR {
140        match self.bits {
141            false => DMAR::Disabled,
142            true => DMAR::Enabled,
143        }
144    }
145    ///DMA mode is disabled for reception
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == DMAR::Disabled
149    }
150    ///DMA mode is enabled for reception
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == DMAR::Enabled
154    }
155}
156///Field `DMAR` writer - DMA enable receiver
157pub type DMAR_W<'a, REG> = crate::BitWriter<'a, REG, DMAR>;
158impl<'a, REG> DMAR_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///DMA mode is disabled for reception
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(DMAR::Disabled)
166    }
167    ///DMA mode is enabled for reception
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(DMAR::Enabled)
171    }
172}
173/**DMA enable transmitter
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum DMAT {
179    ///0: DMA mode is disabled for transmission
180    Disabled = 0,
181    ///1: DMA mode is enabled for transmission
182    Enabled = 1,
183}
184impl From<DMAT> for bool {
185    #[inline(always)]
186    fn from(variant: DMAT) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `DMAT` reader - DMA enable transmitter
191pub type DMAT_R = crate::BitReader<DMAT>;
192impl DMAT_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> DMAT {
196        match self.bits {
197            false => DMAT::Disabled,
198            true => DMAT::Enabled,
199        }
200    }
201    ///DMA mode is disabled for transmission
202    #[inline(always)]
203    pub fn is_disabled(&self) -> bool {
204        *self == DMAT::Disabled
205    }
206    ///DMA mode is enabled for transmission
207    #[inline(always)]
208    pub fn is_enabled(&self) -> bool {
209        *self == DMAT::Enabled
210    }
211}
212///Field `DMAT` writer - DMA enable transmitter
213pub type DMAT_W<'a, REG> = crate::BitWriter<'a, REG, DMAT>;
214impl<'a, REG> DMAT_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///DMA mode is disabled for transmission
219    #[inline(always)]
220    pub fn disabled(self) -> &'a mut crate::W<REG> {
221        self.variant(DMAT::Disabled)
222    }
223    ///DMA mode is enabled for transmission
224    #[inline(always)]
225    pub fn enabled(self) -> &'a mut crate::W<REG> {
226        self.variant(DMAT::Enabled)
227    }
228}
229/**RTS enable
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum RTSE {
235    ///0: RTS hardware flow control disabled
236    Disabled = 0,
237    ///1: RTS output enabled, data is only requested when there is space in the receive buffer
238    Enabled = 1,
239}
240impl From<RTSE> for bool {
241    #[inline(always)]
242    fn from(variant: RTSE) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `RTSE` reader - RTS enable
247pub type RTSE_R = crate::BitReader<RTSE>;
248impl RTSE_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> RTSE {
252        match self.bits {
253            false => RTSE::Disabled,
254            true => RTSE::Enabled,
255        }
256    }
257    ///RTS hardware flow control disabled
258    #[inline(always)]
259    pub fn is_disabled(&self) -> bool {
260        *self == RTSE::Disabled
261    }
262    ///RTS output enabled, data is only requested when there is space in the receive buffer
263    #[inline(always)]
264    pub fn is_enabled(&self) -> bool {
265        *self == RTSE::Enabled
266    }
267}
268///Field `RTSE` writer - RTS enable
269pub type RTSE_W<'a, REG> = crate::BitWriter<'a, REG, RTSE>;
270impl<'a, REG> RTSE_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///RTS hardware flow control disabled
275    #[inline(always)]
276    pub fn disabled(self) -> &'a mut crate::W<REG> {
277        self.variant(RTSE::Disabled)
278    }
279    ///RTS output enabled, data is only requested when there is space in the receive buffer
280    #[inline(always)]
281    pub fn enabled(self) -> &'a mut crate::W<REG> {
282        self.variant(RTSE::Enabled)
283    }
284}
285/**CTS enable
286
287Value on reset: 0*/
288#[cfg_attr(feature = "defmt", derive(defmt::Format))]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290pub enum CTSE {
291    ///0: CTS hardware flow control disabled
292    Disabled = 0,
293    ///1: CTS mode enabled, data is only transmitted when the CTS input is asserted
294    Enabled = 1,
295}
296impl From<CTSE> for bool {
297    #[inline(always)]
298    fn from(variant: CTSE) -> Self {
299        variant as u8 != 0
300    }
301}
302///Field `CTSE` reader - CTS enable
303pub type CTSE_R = crate::BitReader<CTSE>;
304impl CTSE_R {
305    ///Get enumerated values variant
306    #[inline(always)]
307    pub const fn variant(&self) -> CTSE {
308        match self.bits {
309            false => CTSE::Disabled,
310            true => CTSE::Enabled,
311        }
312    }
313    ///CTS hardware flow control disabled
314    #[inline(always)]
315    pub fn is_disabled(&self) -> bool {
316        *self == CTSE::Disabled
317    }
318    ///CTS mode enabled, data is only transmitted when the CTS input is asserted
319    #[inline(always)]
320    pub fn is_enabled(&self) -> bool {
321        *self == CTSE::Enabled
322    }
323}
324///Field `CTSE` writer - CTS enable
325pub type CTSE_W<'a, REG> = crate::BitWriter<'a, REG, CTSE>;
326impl<'a, REG> CTSE_W<'a, REG>
327where
328    REG: crate::Writable + crate::RegisterSpec,
329{
330    ///CTS hardware flow control disabled
331    #[inline(always)]
332    pub fn disabled(self) -> &'a mut crate::W<REG> {
333        self.variant(CTSE::Disabled)
334    }
335    ///CTS mode enabled, data is only transmitted when the CTS input is asserted
336    #[inline(always)]
337    pub fn enabled(self) -> &'a mut crate::W<REG> {
338        self.variant(CTSE::Enabled)
339    }
340}
341/**CTS interrupt enable
342
343Value on reset: 0*/
344#[cfg_attr(feature = "defmt", derive(defmt::Format))]
345#[derive(Clone, Copy, Debug, PartialEq, Eq)]
346pub enum CTSIE {
347    ///0: Interrupt is inhibited
348    Disabled = 0,
349    ///1: An interrupt is generated whenever CTSIF=1 in the ISR register
350    Enabled = 1,
351}
352impl From<CTSIE> for bool {
353    #[inline(always)]
354    fn from(variant: CTSIE) -> Self {
355        variant as u8 != 0
356    }
357}
358///Field `CTSIE` reader - CTS interrupt enable
359pub type CTSIE_R = crate::BitReader<CTSIE>;
360impl CTSIE_R {
361    ///Get enumerated values variant
362    #[inline(always)]
363    pub const fn variant(&self) -> CTSIE {
364        match self.bits {
365            false => CTSIE::Disabled,
366            true => CTSIE::Enabled,
367        }
368    }
369    ///Interrupt is inhibited
370    #[inline(always)]
371    pub fn is_disabled(&self) -> bool {
372        *self == CTSIE::Disabled
373    }
374    ///An interrupt is generated whenever CTSIF=1 in the ISR register
375    #[inline(always)]
376    pub fn is_enabled(&self) -> bool {
377        *self == CTSIE::Enabled
378    }
379}
380///Field `CTSIE` writer - CTS interrupt enable
381pub type CTSIE_W<'a, REG> = crate::BitWriter<'a, REG, CTSIE>;
382impl<'a, REG> CTSIE_W<'a, REG>
383where
384    REG: crate::Writable + crate::RegisterSpec,
385{
386    ///Interrupt is inhibited
387    #[inline(always)]
388    pub fn disabled(self) -> &'a mut crate::W<REG> {
389        self.variant(CTSIE::Disabled)
390    }
391    ///An interrupt is generated whenever CTSIF=1 in the ISR register
392    #[inline(always)]
393    pub fn enabled(self) -> &'a mut crate::W<REG> {
394        self.variant(CTSIE::Enabled)
395    }
396}
397/**Overrun Disable
398
399Value on reset: 0*/
400#[cfg_attr(feature = "defmt", derive(defmt::Format))]
401#[derive(Clone, Copy, Debug, PartialEq, Eq)]
402pub enum OVRDIS {
403    ///0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
404    Enabled = 0,
405    ///1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
406    Disabled = 1,
407}
408impl From<OVRDIS> for bool {
409    #[inline(always)]
410    fn from(variant: OVRDIS) -> Self {
411        variant as u8 != 0
412    }
413}
414///Field `OVRDIS` reader - Overrun Disable
415pub type OVRDIS_R = crate::BitReader<OVRDIS>;
416impl OVRDIS_R {
417    ///Get enumerated values variant
418    #[inline(always)]
419    pub const fn variant(&self) -> OVRDIS {
420        match self.bits {
421            false => OVRDIS::Enabled,
422            true => OVRDIS::Disabled,
423        }
424    }
425    ///Overrun Error Flag, ORE, is set when received data is not read before receiving new data
426    #[inline(always)]
427    pub fn is_enabled(&self) -> bool {
428        *self == OVRDIS::Enabled
429    }
430    ///Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
431    #[inline(always)]
432    pub fn is_disabled(&self) -> bool {
433        *self == OVRDIS::Disabled
434    }
435}
436///Field `OVRDIS` writer - Overrun Disable
437pub type OVRDIS_W<'a, REG> = crate::BitWriter<'a, REG, OVRDIS>;
438impl<'a, REG> OVRDIS_W<'a, REG>
439where
440    REG: crate::Writable + crate::RegisterSpec,
441{
442    ///Overrun Error Flag, ORE, is set when received data is not read before receiving new data
443    #[inline(always)]
444    pub fn enabled(self) -> &'a mut crate::W<REG> {
445        self.variant(OVRDIS::Enabled)
446    }
447    ///Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
448    #[inline(always)]
449    pub fn disabled(self) -> &'a mut crate::W<REG> {
450        self.variant(OVRDIS::Disabled)
451    }
452}
453/**DMA Disable on Reception Error
454
455Value on reset: 0*/
456#[cfg_attr(feature = "defmt", derive(defmt::Format))]
457#[derive(Clone, Copy, Debug, PartialEq, Eq)]
458pub enum DDRE {
459    ///0: DMA is not disabled in case of reception error
460    NotDisabled = 0,
461    ///1: DMA is disabled following a reception error
462    Disabled = 1,
463}
464impl From<DDRE> for bool {
465    #[inline(always)]
466    fn from(variant: DDRE) -> Self {
467        variant as u8 != 0
468    }
469}
470///Field `DDRE` reader - DMA Disable on Reception Error
471pub type DDRE_R = crate::BitReader<DDRE>;
472impl DDRE_R {
473    ///Get enumerated values variant
474    #[inline(always)]
475    pub const fn variant(&self) -> DDRE {
476        match self.bits {
477            false => DDRE::NotDisabled,
478            true => DDRE::Disabled,
479        }
480    }
481    ///DMA is not disabled in case of reception error
482    #[inline(always)]
483    pub fn is_not_disabled(&self) -> bool {
484        *self == DDRE::NotDisabled
485    }
486    ///DMA is disabled following a reception error
487    #[inline(always)]
488    pub fn is_disabled(&self) -> bool {
489        *self == DDRE::Disabled
490    }
491}
492///Field `DDRE` writer - DMA Disable on Reception Error
493pub type DDRE_W<'a, REG> = crate::BitWriter<'a, REG, DDRE>;
494impl<'a, REG> DDRE_W<'a, REG>
495where
496    REG: crate::Writable + crate::RegisterSpec,
497{
498    ///DMA is not disabled in case of reception error
499    #[inline(always)]
500    pub fn not_disabled(self) -> &'a mut crate::W<REG> {
501        self.variant(DDRE::NotDisabled)
502    }
503    ///DMA is disabled following a reception error
504    #[inline(always)]
505    pub fn disabled(self) -> &'a mut crate::W<REG> {
506        self.variant(DDRE::Disabled)
507    }
508}
509/**Driver enable mode
510
511Value on reset: 0*/
512#[cfg_attr(feature = "defmt", derive(defmt::Format))]
513#[derive(Clone, Copy, Debug, PartialEq, Eq)]
514pub enum DEM {
515    ///0: DE function is disabled
516    Disabled = 0,
517    ///1: The DE signal is output on the RTS pin
518    Enabled = 1,
519}
520impl From<DEM> for bool {
521    #[inline(always)]
522    fn from(variant: DEM) -> Self {
523        variant as u8 != 0
524    }
525}
526///Field `DEM` reader - Driver enable mode
527pub type DEM_R = crate::BitReader<DEM>;
528impl DEM_R {
529    ///Get enumerated values variant
530    #[inline(always)]
531    pub const fn variant(&self) -> DEM {
532        match self.bits {
533            false => DEM::Disabled,
534            true => DEM::Enabled,
535        }
536    }
537    ///DE function is disabled
538    #[inline(always)]
539    pub fn is_disabled(&self) -> bool {
540        *self == DEM::Disabled
541    }
542    ///The DE signal is output on the RTS pin
543    #[inline(always)]
544    pub fn is_enabled(&self) -> bool {
545        *self == DEM::Enabled
546    }
547}
548///Field `DEM` writer - Driver enable mode
549pub type DEM_W<'a, REG> = crate::BitWriter<'a, REG, DEM>;
550impl<'a, REG> DEM_W<'a, REG>
551where
552    REG: crate::Writable + crate::RegisterSpec,
553{
554    ///DE function is disabled
555    #[inline(always)]
556    pub fn disabled(self) -> &'a mut crate::W<REG> {
557        self.variant(DEM::Disabled)
558    }
559    ///The DE signal is output on the RTS pin
560    #[inline(always)]
561    pub fn enabled(self) -> &'a mut crate::W<REG> {
562        self.variant(DEM::Enabled)
563    }
564}
565/**Driver enable polarity selection
566
567Value on reset: 0*/
568#[cfg_attr(feature = "defmt", derive(defmt::Format))]
569#[derive(Clone, Copy, Debug, PartialEq, Eq)]
570pub enum DEP {
571    ///0: DE signal is active high
572    High = 0,
573    ///1: DE signal is active low
574    Low = 1,
575}
576impl From<DEP> for bool {
577    #[inline(always)]
578    fn from(variant: DEP) -> Self {
579        variant as u8 != 0
580    }
581}
582///Field `DEP` reader - Driver enable polarity selection
583pub type DEP_R = crate::BitReader<DEP>;
584impl DEP_R {
585    ///Get enumerated values variant
586    #[inline(always)]
587    pub const fn variant(&self) -> DEP {
588        match self.bits {
589            false => DEP::High,
590            true => DEP::Low,
591        }
592    }
593    ///DE signal is active high
594    #[inline(always)]
595    pub fn is_high(&self) -> bool {
596        *self == DEP::High
597    }
598    ///DE signal is active low
599    #[inline(always)]
600    pub fn is_low(&self) -> bool {
601        *self == DEP::Low
602    }
603}
604///Field `DEP` writer - Driver enable polarity selection
605pub type DEP_W<'a, REG> = crate::BitWriter<'a, REG, DEP>;
606impl<'a, REG> DEP_W<'a, REG>
607where
608    REG: crate::Writable + crate::RegisterSpec,
609{
610    ///DE signal is active high
611    #[inline(always)]
612    pub fn high(self) -> &'a mut crate::W<REG> {
613        self.variant(DEP::High)
614    }
615    ///DE signal is active low
616    #[inline(always)]
617    pub fn low(self) -> &'a mut crate::W<REG> {
618        self.variant(DEP::Low)
619    }
620}
621/**Wakeup from Stop mode interrupt flag selection
622
623Value on reset: 0*/
624#[cfg_attr(feature = "defmt", derive(defmt::Format))]
625#[derive(Clone, Copy, Debug, PartialEq, Eq)]
626#[repr(u8)]
627pub enum WUS {
628    ///0: WUF active on address match
629    Address = 0,
630    ///2: WuF active on Start bit detection
631    Start = 2,
632    ///3: WUF active on RXNE
633    Rxne = 3,
634}
635impl From<WUS> for u8 {
636    #[inline(always)]
637    fn from(variant: WUS) -> Self {
638        variant as _
639    }
640}
641impl crate::FieldSpec for WUS {
642    type Ux = u8;
643}
644impl crate::IsEnum for WUS {}
645///Field `WUS` reader - Wakeup from Stop mode interrupt flag selection
646pub type WUS_R = crate::FieldReader<WUS>;
647impl WUS_R {
648    ///Get enumerated values variant
649    #[inline(always)]
650    pub const fn variant(&self) -> Option<WUS> {
651        match self.bits {
652            0 => Some(WUS::Address),
653            2 => Some(WUS::Start),
654            3 => Some(WUS::Rxne),
655            _ => None,
656        }
657    }
658    ///WUF active on address match
659    #[inline(always)]
660    pub fn is_address(&self) -> bool {
661        *self == WUS::Address
662    }
663    ///WuF active on Start bit detection
664    #[inline(always)]
665    pub fn is_start(&self) -> bool {
666        *self == WUS::Start
667    }
668    ///WUF active on RXNE
669    #[inline(always)]
670    pub fn is_rxne(&self) -> bool {
671        *self == WUS::Rxne
672    }
673}
674///Field `WUS` writer - Wakeup from Stop mode interrupt flag selection
675pub type WUS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, WUS>;
676impl<'a, REG> WUS_W<'a, REG>
677where
678    REG: crate::Writable + crate::RegisterSpec,
679    REG::Ux: From<u8>,
680{
681    ///WUF active on address match
682    #[inline(always)]
683    pub fn address(self) -> &'a mut crate::W<REG> {
684        self.variant(WUS::Address)
685    }
686    ///WuF active on Start bit detection
687    #[inline(always)]
688    pub fn start(self) -> &'a mut crate::W<REG> {
689        self.variant(WUS::Start)
690    }
691    ///WUF active on RXNE
692    #[inline(always)]
693    pub fn rxne(self) -> &'a mut crate::W<REG> {
694        self.variant(WUS::Rxne)
695    }
696}
697/**Wakeup from Stop mode interrupt enable
698
699Value on reset: 0*/
700#[cfg_attr(feature = "defmt", derive(defmt::Format))]
701#[derive(Clone, Copy, Debug, PartialEq, Eq)]
702pub enum WUFIE {
703    ///0: Interrupt is inhibited
704    Disabled = 0,
705    ///1: An USART interrupt is generated whenever WUF=1 in the ISR register
706    Enabled = 1,
707}
708impl From<WUFIE> for bool {
709    #[inline(always)]
710    fn from(variant: WUFIE) -> Self {
711        variant as u8 != 0
712    }
713}
714///Field `WUFIE` reader - Wakeup from Stop mode interrupt enable
715pub type WUFIE_R = crate::BitReader<WUFIE>;
716impl WUFIE_R {
717    ///Get enumerated values variant
718    #[inline(always)]
719    pub const fn variant(&self) -> WUFIE {
720        match self.bits {
721            false => WUFIE::Disabled,
722            true => WUFIE::Enabled,
723        }
724    }
725    ///Interrupt is inhibited
726    #[inline(always)]
727    pub fn is_disabled(&self) -> bool {
728        *self == WUFIE::Disabled
729    }
730    ///An USART interrupt is generated whenever WUF=1 in the ISR register
731    #[inline(always)]
732    pub fn is_enabled(&self) -> bool {
733        *self == WUFIE::Enabled
734    }
735}
736///Field `WUFIE` writer - Wakeup from Stop mode interrupt enable
737pub type WUFIE_W<'a, REG> = crate::BitWriter<'a, REG, WUFIE>;
738impl<'a, REG> WUFIE_W<'a, REG>
739where
740    REG: crate::Writable + crate::RegisterSpec,
741{
742    ///Interrupt is inhibited
743    #[inline(always)]
744    pub fn disabled(self) -> &'a mut crate::W<REG> {
745        self.variant(WUFIE::Disabled)
746    }
747    ///An USART interrupt is generated whenever WUF=1 in the ISR register
748    #[inline(always)]
749    pub fn enabled(self) -> &'a mut crate::W<REG> {
750        self.variant(WUFIE::Enabled)
751    }
752}
753impl R {
754    ///Bit 0 - Error interrupt enable
755    #[inline(always)]
756    pub fn eie(&self) -> EIE_R {
757        EIE_R::new((self.bits & 1) != 0)
758    }
759    ///Bit 3 - Half-duplex selection
760    #[inline(always)]
761    pub fn hdsel(&self) -> HDSEL_R {
762        HDSEL_R::new(((self.bits >> 3) & 1) != 0)
763    }
764    ///Bit 6 - DMA enable receiver
765    #[inline(always)]
766    pub fn dmar(&self) -> DMAR_R {
767        DMAR_R::new(((self.bits >> 6) & 1) != 0)
768    }
769    ///Bit 7 - DMA enable transmitter
770    #[inline(always)]
771    pub fn dmat(&self) -> DMAT_R {
772        DMAT_R::new(((self.bits >> 7) & 1) != 0)
773    }
774    ///Bit 8 - RTS enable
775    #[inline(always)]
776    pub fn rtse(&self) -> RTSE_R {
777        RTSE_R::new(((self.bits >> 8) & 1) != 0)
778    }
779    ///Bit 9 - CTS enable
780    #[inline(always)]
781    pub fn ctse(&self) -> CTSE_R {
782        CTSE_R::new(((self.bits >> 9) & 1) != 0)
783    }
784    ///Bit 10 - CTS interrupt enable
785    #[inline(always)]
786    pub fn ctsie(&self) -> CTSIE_R {
787        CTSIE_R::new(((self.bits >> 10) & 1) != 0)
788    }
789    ///Bit 12 - Overrun Disable
790    #[inline(always)]
791    pub fn ovrdis(&self) -> OVRDIS_R {
792        OVRDIS_R::new(((self.bits >> 12) & 1) != 0)
793    }
794    ///Bit 13 - DMA Disable on Reception Error
795    #[inline(always)]
796    pub fn ddre(&self) -> DDRE_R {
797        DDRE_R::new(((self.bits >> 13) & 1) != 0)
798    }
799    ///Bit 14 - Driver enable mode
800    #[inline(always)]
801    pub fn dem(&self) -> DEM_R {
802        DEM_R::new(((self.bits >> 14) & 1) != 0)
803    }
804    ///Bit 15 - Driver enable polarity selection
805    #[inline(always)]
806    pub fn dep(&self) -> DEP_R {
807        DEP_R::new(((self.bits >> 15) & 1) != 0)
808    }
809    ///Bits 20:21 - Wakeup from Stop mode interrupt flag selection
810    #[inline(always)]
811    pub fn wus(&self) -> WUS_R {
812        WUS_R::new(((self.bits >> 20) & 3) as u8)
813    }
814    ///Bit 22 - Wakeup from Stop mode interrupt enable
815    #[inline(always)]
816    pub fn wufie(&self) -> WUFIE_R {
817        WUFIE_R::new(((self.bits >> 22) & 1) != 0)
818    }
819}
820impl core::fmt::Debug for R {
821    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
822        f.debug_struct("CR3")
823            .field("wufie", &self.wufie())
824            .field("wus", &self.wus())
825            .field("dep", &self.dep())
826            .field("dem", &self.dem())
827            .field("ddre", &self.ddre())
828            .field("ovrdis", &self.ovrdis())
829            .field("ctsie", &self.ctsie())
830            .field("ctse", &self.ctse())
831            .field("rtse", &self.rtse())
832            .field("dmat", &self.dmat())
833            .field("dmar", &self.dmar())
834            .field("hdsel", &self.hdsel())
835            .field("eie", &self.eie())
836            .finish()
837    }
838}
839impl W {
840    ///Bit 0 - Error interrupt enable
841    #[inline(always)]
842    pub fn eie(&mut self) -> EIE_W<CR3rs> {
843        EIE_W::new(self, 0)
844    }
845    ///Bit 3 - Half-duplex selection
846    #[inline(always)]
847    pub fn hdsel(&mut self) -> HDSEL_W<CR3rs> {
848        HDSEL_W::new(self, 3)
849    }
850    ///Bit 6 - DMA enable receiver
851    #[inline(always)]
852    pub fn dmar(&mut self) -> DMAR_W<CR3rs> {
853        DMAR_W::new(self, 6)
854    }
855    ///Bit 7 - DMA enable transmitter
856    #[inline(always)]
857    pub fn dmat(&mut self) -> DMAT_W<CR3rs> {
858        DMAT_W::new(self, 7)
859    }
860    ///Bit 8 - RTS enable
861    #[inline(always)]
862    pub fn rtse(&mut self) -> RTSE_W<CR3rs> {
863        RTSE_W::new(self, 8)
864    }
865    ///Bit 9 - CTS enable
866    #[inline(always)]
867    pub fn ctse(&mut self) -> CTSE_W<CR3rs> {
868        CTSE_W::new(self, 9)
869    }
870    ///Bit 10 - CTS interrupt enable
871    #[inline(always)]
872    pub fn ctsie(&mut self) -> CTSIE_W<CR3rs> {
873        CTSIE_W::new(self, 10)
874    }
875    ///Bit 12 - Overrun Disable
876    #[inline(always)]
877    pub fn ovrdis(&mut self) -> OVRDIS_W<CR3rs> {
878        OVRDIS_W::new(self, 12)
879    }
880    ///Bit 13 - DMA Disable on Reception Error
881    #[inline(always)]
882    pub fn ddre(&mut self) -> DDRE_W<CR3rs> {
883        DDRE_W::new(self, 13)
884    }
885    ///Bit 14 - Driver enable mode
886    #[inline(always)]
887    pub fn dem(&mut self) -> DEM_W<CR3rs> {
888        DEM_W::new(self, 14)
889    }
890    ///Bit 15 - Driver enable polarity selection
891    #[inline(always)]
892    pub fn dep(&mut self) -> DEP_W<CR3rs> {
893        DEP_W::new(self, 15)
894    }
895    ///Bits 20:21 - Wakeup from Stop mode interrupt flag selection
896    #[inline(always)]
897    pub fn wus(&mut self) -> WUS_W<CR3rs> {
898        WUS_W::new(self, 20)
899    }
900    ///Bit 22 - Wakeup from Stop mode interrupt enable
901    #[inline(always)]
902    pub fn wufie(&mut self) -> WUFIE_W<CR3rs> {
903        WUFIE_W::new(self, 22)
904    }
905}
906/**Control register 3
907
908You can [`read`](crate::Reg::read) this register and get [`cr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
909
910See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#LPUART1:CR3)*/
911pub struct CR3rs;
912impl crate::RegisterSpec for CR3rs {
913    type Ux = u32;
914}
915///`read()` method returns [`cr3::R`](R) reader structure
916impl crate::Readable for CR3rs {}
917///`write(|w| ..)` method takes [`cr3::W`](W) writer structure
918impl crate::Writable for CR3rs {
919    type Safety = crate::Unsafe;
920}
921///`reset()` method sets CR3 to value 0
922impl crate::Resettable for CR3rs {}
stm32l4/stm32l4x5/lpuart1/cr3.rs

stm32l4/stm32l4x5/lpuart1/
cr3.rs
