stm32l4/stm32l4x5/i2c1/
oar2.rs

1///Register `OAR2` reader
2pub type R = crate::R<OAR2rs>;
3///Register `OAR2` writer
4pub type W = crate::W<OAR2rs>;
5///Field `OA2` reader - Interface address
6pub type OA2_R = crate::FieldReader;
7///Field `OA2` writer - Interface address
8pub type OA2_W<'a, REG> = crate::FieldWriter<'a, REG, 7, u8, crate::Safe>;
9/**Own Address 2 masks
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14#[repr(u8)]
15pub enum OA2MSK {
16    ///0: No mask
17    NoMask = 0,
18    ///1: OA2\[1\] is masked and don’t care. Only OA2\[7:2\] are compared
19    Mask1 = 1,
20    ///2: OA2\[2:1\] are masked and don’t care. Only OA2\[7:3\] are compared
21    Mask2 = 2,
22    ///3: OA2\[3:1\] are masked and don’t care. Only OA2\[7:4\] are compared
23    Mask3 = 3,
24    ///4: OA2\[4:1\] are masked and don’t care. Only OA2\[7:5\] are compared
25    Mask4 = 4,
26    ///5: OA2\[5:1\] are masked and don’t care. Only OA2\[7:6\] are compared
27    Mask5 = 5,
28    ///6: OA2\[6:1\] are masked and don’t care. Only OA2\[7\] is compared.
29    Mask6 = 6,
30    ///7: OA2\[7:1\] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
31    Mask7 = 7,
32}
33impl From<OA2MSK> for u8 {
34    #[inline(always)]
35    fn from(variant: OA2MSK) -> Self {
36        variant as _
37    }
38}
39impl crate::FieldSpec for OA2MSK {
40    type Ux = u8;
41}
42impl crate::IsEnum for OA2MSK {}
43///Field `OA2MSK` reader - Own Address 2 masks
44pub type OA2MSK_R = crate::FieldReader<OA2MSK>;
45impl OA2MSK_R {
46    ///Get enumerated values variant
47    #[inline(always)]
48    pub const fn variant(&self) -> OA2MSK {
49        match self.bits {
50            0 => OA2MSK::NoMask,
51            1 => OA2MSK::Mask1,
52            2 => OA2MSK::Mask2,
53            3 => OA2MSK::Mask3,
54            4 => OA2MSK::Mask4,
55            5 => OA2MSK::Mask5,
56            6 => OA2MSK::Mask6,
57            7 => OA2MSK::Mask7,
58            _ => unreachable!(),
59        }
60    }
61    ///No mask
62    #[inline(always)]
63    pub fn is_no_mask(&self) -> bool {
64        *self == OA2MSK::NoMask
65    }
66    ///OA2\[1\] is masked and don’t care. Only OA2\[7:2\] are compared
67    #[inline(always)]
68    pub fn is_mask1(&self) -> bool {
69        *self == OA2MSK::Mask1
70    }
71    ///OA2\[2:1\] are masked and don’t care. Only OA2\[7:3\] are compared
72    #[inline(always)]
73    pub fn is_mask2(&self) -> bool {
74        *self == OA2MSK::Mask2
75    }
76    ///OA2\[3:1\] are masked and don’t care. Only OA2\[7:4\] are compared
77    #[inline(always)]
78    pub fn is_mask3(&self) -> bool {
79        *self == OA2MSK::Mask3
80    }
81    ///OA2\[4:1\] are masked and don’t care. Only OA2\[7:5\] are compared
82    #[inline(always)]
83    pub fn is_mask4(&self) -> bool {
84        *self == OA2MSK::Mask4
85    }
86    ///OA2\[5:1\] are masked and don’t care. Only OA2\[7:6\] are compared
87    #[inline(always)]
88    pub fn is_mask5(&self) -> bool {
89        *self == OA2MSK::Mask5
90    }
91    ///OA2\[6:1\] are masked and don’t care. Only OA2\[7\] is compared.
92    #[inline(always)]
93    pub fn is_mask6(&self) -> bool {
94        *self == OA2MSK::Mask6
95    }
96    ///OA2\[7:1\] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
97    #[inline(always)]
98    pub fn is_mask7(&self) -> bool {
99        *self == OA2MSK::Mask7
100    }
101}
102///Field `OA2MSK` writer - Own Address 2 masks
103pub type OA2MSK_W<'a, REG> = crate::FieldWriter<'a, REG, 3, OA2MSK, crate::Safe>;
104impl<'a, REG> OA2MSK_W<'a, REG>
105where
106    REG: crate::Writable + crate::RegisterSpec,
107    REG::Ux: From<u8>,
108{
109    ///No mask
110    #[inline(always)]
111    pub fn no_mask(self) -> &'a mut crate::W<REG> {
112        self.variant(OA2MSK::NoMask)
113    }
114    ///OA2\[1\] is masked and don’t care. Only OA2\[7:2\] are compared
115    #[inline(always)]
116    pub fn mask1(self) -> &'a mut crate::W<REG> {
117        self.variant(OA2MSK::Mask1)
118    }
119    ///OA2\[2:1\] are masked and don’t care. Only OA2\[7:3\] are compared
120    #[inline(always)]
121    pub fn mask2(self) -> &'a mut crate::W<REG> {
122        self.variant(OA2MSK::Mask2)
123    }
124    ///OA2\[3:1\] are masked and don’t care. Only OA2\[7:4\] are compared
125    #[inline(always)]
126    pub fn mask3(self) -> &'a mut crate::W<REG> {
127        self.variant(OA2MSK::Mask3)
128    }
129    ///OA2\[4:1\] are masked and don’t care. Only OA2\[7:5\] are compared
130    #[inline(always)]
131    pub fn mask4(self) -> &'a mut crate::W<REG> {
132        self.variant(OA2MSK::Mask4)
133    }
134    ///OA2\[5:1\] are masked and don’t care. Only OA2\[7:6\] are compared
135    #[inline(always)]
136    pub fn mask5(self) -> &'a mut crate::W<REG> {
137        self.variant(OA2MSK::Mask5)
138    }
139    ///OA2\[6:1\] are masked and don’t care. Only OA2\[7\] is compared.
140    #[inline(always)]
141    pub fn mask6(self) -> &'a mut crate::W<REG> {
142        self.variant(OA2MSK::Mask6)
143    }
144    ///OA2\[7:1\] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
145    #[inline(always)]
146    pub fn mask7(self) -> &'a mut crate::W<REG> {
147        self.variant(OA2MSK::Mask7)
148    }
149}
150/**Own Address 2 enable
151
152Value on reset: 0*/
153#[cfg_attr(feature = "defmt", derive(defmt::Format))]
154#[derive(Clone, Copy, Debug, PartialEq, Eq)]
155pub enum OA2EN {
156    ///0: Own address 2 disabled. The received slave address OA2 is NACKed
157    Disabled = 0,
158    ///1: Own address 2 enabled. The received slave address OA2 is ACKed
159    Enabled = 1,
160}
161impl From<OA2EN> for bool {
162    #[inline(always)]
163    fn from(variant: OA2EN) -> Self {
164        variant as u8 != 0
165    }
166}
167///Field `OA2EN` reader - Own Address 2 enable
168pub type OA2EN_R = crate::BitReader<OA2EN>;
169impl OA2EN_R {
170    ///Get enumerated values variant
171    #[inline(always)]
172    pub const fn variant(&self) -> OA2EN {
173        match self.bits {
174            false => OA2EN::Disabled,
175            true => OA2EN::Enabled,
176        }
177    }
178    ///Own address 2 disabled. The received slave address OA2 is NACKed
179    #[inline(always)]
180    pub fn is_disabled(&self) -> bool {
181        *self == OA2EN::Disabled
182    }
183    ///Own address 2 enabled. The received slave address OA2 is ACKed
184    #[inline(always)]
185    pub fn is_enabled(&self) -> bool {
186        *self == OA2EN::Enabled
187    }
188}
189///Field `OA2EN` writer - Own Address 2 enable
190pub type OA2EN_W<'a, REG> = crate::BitWriter<'a, REG, OA2EN>;
191impl<'a, REG> OA2EN_W<'a, REG>
192where
193    REG: crate::Writable + crate::RegisterSpec,
194{
195    ///Own address 2 disabled. The received slave address OA2 is NACKed
196    #[inline(always)]
197    pub fn disabled(self) -> &'a mut crate::W<REG> {
198        self.variant(OA2EN::Disabled)
199    }
200    ///Own address 2 enabled. The received slave address OA2 is ACKed
201    #[inline(always)]
202    pub fn enabled(self) -> &'a mut crate::W<REG> {
203        self.variant(OA2EN::Enabled)
204    }
205}
206impl R {
207    ///Bits 1:7 - Interface address
208    #[inline(always)]
209    pub fn oa2(&self) -> OA2_R {
210        OA2_R::new(((self.bits >> 1) & 0x7f) as u8)
211    }
212    ///Bits 8:10 - Own Address 2 masks
213    #[inline(always)]
214    pub fn oa2msk(&self) -> OA2MSK_R {
215        OA2MSK_R::new(((self.bits >> 8) & 7) as u8)
216    }
217    ///Bit 15 - Own Address 2 enable
218    #[inline(always)]
219    pub fn oa2en(&self) -> OA2EN_R {
220        OA2EN_R::new(((self.bits >> 15) & 1) != 0)
221    }
222}
223impl core::fmt::Debug for R {
224    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
225        f.debug_struct("OAR2")
226            .field("oa2", &self.oa2())
227            .field("oa2msk", &self.oa2msk())
228            .field("oa2en", &self.oa2en())
229            .finish()
230    }
231}
232impl W {
233    ///Bits 1:7 - Interface address
234    #[inline(always)]
235    pub fn oa2(&mut self) -> OA2_W<OAR2rs> {
236        OA2_W::new(self, 1)
237    }
238    ///Bits 8:10 - Own Address 2 masks
239    #[inline(always)]
240    pub fn oa2msk(&mut self) -> OA2MSK_W<OAR2rs> {
241        OA2MSK_W::new(self, 8)
242    }
243    ///Bit 15 - Own Address 2 enable
244    #[inline(always)]
245    pub fn oa2en(&mut self) -> OA2EN_W<OAR2rs> {
246        OA2EN_W::new(self, 15)
247    }
248}
249/**Own address register 2
250
251You can [`read`](crate::Reg::read) this register and get [`oar2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`oar2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
252
253See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#I2C1:OAR2)*/
254pub struct OAR2rs;
255impl crate::RegisterSpec for OAR2rs {
256    type Ux = u32;
257}
258///`read()` method returns [`oar2::R`](R) reader structure
259impl crate::Readable for OAR2rs {}
260///`write(|w| ..)` method takes [`oar2::W`](W) writer structure
261impl crate::Writable for OAR2rs {
262    type Safety = crate::Unsafe;
263}
264///`reset()` method sets OAR2 to value 0
265impl crate::Resettable for OAR2rs {}
stm32l4/stm32l4x5/i2c1/oar2.rs

stm32l4/stm32l4x5/i2c1/
oar2.rs
