stm32l4/stm32l4x5/fmc/
bcr.rs

1///Register `BCR%s` reader
2pub type R = crate::R<BCRrs>;
3///Register `BCR%s` writer
4pub type W = crate::W<BCRrs>;
5///ASYNCWAIT
6pub use super::bcr1::ASYNCWAIT;
7///Field `ASYNCWAIT` reader - ASYNCWAIT
8pub use super::bcr1::ASYNCWAIT_R;
9///Field `ASYNCWAIT` writer - ASYNCWAIT
10pub use super::bcr1::ASYNCWAIT_W;
11///BURSTEN
12pub use super::bcr1::BURSTEN;
13///Field `BURSTEN` reader - BURSTEN
14pub use super::bcr1::BURSTEN_R;
15///Field `BURSTEN` writer - BURSTEN
16pub use super::bcr1::BURSTEN_W;
17///CBURSTRW
18pub use super::bcr1::CBURSTRW;
19///Field `CBURSTRW` reader - CBURSTRW
20pub use super::bcr1::CBURSTRW_R;
21///Field `CBURSTRW` writer - CBURSTRW
22pub use super::bcr1::CBURSTRW_W;
23///CRAM page size
24pub use super::bcr1::CPSIZE;
25///Field `CPSIZE` reader - CRAM page size
26pub use super::bcr1::CPSIZE_R;
27///Field `CPSIZE` writer - CRAM page size
28pub use super::bcr1::CPSIZE_W;
29///EXTMOD
30pub use super::bcr1::EXTMOD;
31///Field `EXTMOD` reader - EXTMOD
32pub use super::bcr1::EXTMOD_R;
33///Field `EXTMOD` writer - EXTMOD
34pub use super::bcr1::EXTMOD_W;
35///FACCEN
36pub use super::bcr1::FACCEN;
37///Field `FACCEN` reader - FACCEN
38pub use super::bcr1::FACCEN_R;
39///Field `FACCEN` writer - FACCEN
40pub use super::bcr1::FACCEN_W;
41///MBKEN
42pub use super::bcr1::MBKEN;
43///Field `MBKEN` reader - MBKEN
44pub use super::bcr1::MBKEN_R;
45///Field `MBKEN` writer - MBKEN
46pub use super::bcr1::MBKEN_W;
47///MTYP
48pub use super::bcr1::MTYP;
49///Field `MTYP` reader - MTYP
50pub use super::bcr1::MTYP_R;
51///Field `MTYP` writer - MTYP
52pub use super::bcr1::MTYP_W;
53///MUXEN
54pub use super::bcr1::MUXEN;
55///Field `MUXEN` reader - MUXEN
56pub use super::bcr1::MUXEN_R;
57///Field `MUXEN` writer - MUXEN
58pub use super::bcr1::MUXEN_W;
59///MWID
60pub use super::bcr1::MWID;
61///Field `MWID` reader - MWID
62pub use super::bcr1::MWID_R;
63///Field `MWID` writer - MWID
64pub use super::bcr1::MWID_W;
65///WAITCFG
66pub use super::bcr1::WAITCFG;
67///Field `WAITCFG` reader - WAITCFG
68pub use super::bcr1::WAITCFG_R;
69///Field `WAITCFG` writer - WAITCFG
70pub use super::bcr1::WAITCFG_W;
71///WAITEN
72pub use super::bcr1::WAITEN;
73///Field `WAITEN` reader - WAITEN
74pub use super::bcr1::WAITEN_R;
75///Field `WAITEN` writer - WAITEN
76pub use super::bcr1::WAITEN_W;
77///WAITPOL
78pub use super::bcr1::WAITPOL;
79///Field `WAITPOL` reader - WAITPOL
80pub use super::bcr1::WAITPOL_R;
81///Field `WAITPOL` writer - WAITPOL
82pub use super::bcr1::WAITPOL_W;
83///WREN
84pub use super::bcr1::WREN;
85///Field `WREN` reader - WREN
86pub use super::bcr1::WREN_R;
87///Field `WREN` writer - WREN
88pub use super::bcr1::WREN_W;
89impl R {
90    ///Bit 0 - MBKEN
91    #[inline(always)]
92    pub fn mbken(&self) -> MBKEN_R {
93        MBKEN_R::new((self.bits & 1) != 0)
94    }
95    ///Bit 1 - MUXEN
96    #[inline(always)]
97    pub fn muxen(&self) -> MUXEN_R {
98        MUXEN_R::new(((self.bits >> 1) & 1) != 0)
99    }
100    ///Bits 2:3 - MTYP
101    #[inline(always)]
102    pub fn mtyp(&self) -> MTYP_R {
103        MTYP_R::new(((self.bits >> 2) & 3) as u8)
104    }
105    ///Bits 4:5 - MWID
106    #[inline(always)]
107    pub fn mwid(&self) -> MWID_R {
108        MWID_R::new(((self.bits >> 4) & 3) as u8)
109    }
110    ///Bit 6 - FACCEN
111    #[inline(always)]
112    pub fn faccen(&self) -> FACCEN_R {
113        FACCEN_R::new(((self.bits >> 6) & 1) != 0)
114    }
115    ///Bit 8 - BURSTEN
116    #[inline(always)]
117    pub fn bursten(&self) -> BURSTEN_R {
118        BURSTEN_R::new(((self.bits >> 8) & 1) != 0)
119    }
120    ///Bit 9 - WAITPOL
121    #[inline(always)]
122    pub fn waitpol(&self) -> WAITPOL_R {
123        WAITPOL_R::new(((self.bits >> 9) & 1) != 0)
124    }
125    ///Bit 11 - WAITCFG
126    #[inline(always)]
127    pub fn waitcfg(&self) -> WAITCFG_R {
128        WAITCFG_R::new(((self.bits >> 11) & 1) != 0)
129    }
130    ///Bit 12 - WREN
131    #[inline(always)]
132    pub fn wren(&self) -> WREN_R {
133        WREN_R::new(((self.bits >> 12) & 1) != 0)
134    }
135    ///Bit 13 - WAITEN
136    #[inline(always)]
137    pub fn waiten(&self) -> WAITEN_R {
138        WAITEN_R::new(((self.bits >> 13) & 1) != 0)
139    }
140    ///Bit 14 - EXTMOD
141    #[inline(always)]
142    pub fn extmod(&self) -> EXTMOD_R {
143        EXTMOD_R::new(((self.bits >> 14) & 1) != 0)
144    }
145    ///Bit 15 - ASYNCWAIT
146    #[inline(always)]
147    pub fn asyncwait(&self) -> ASYNCWAIT_R {
148        ASYNCWAIT_R::new(((self.bits >> 15) & 1) != 0)
149    }
150    ///Bits 16:18 - CRAM page size
151    #[inline(always)]
152    pub fn cpsize(&self) -> CPSIZE_R {
153        CPSIZE_R::new(((self.bits >> 16) & 7) as u8)
154    }
155    ///Bit 19 - CBURSTRW
156    #[inline(always)]
157    pub fn cburstrw(&self) -> CBURSTRW_R {
158        CBURSTRW_R::new(((self.bits >> 19) & 1) != 0)
159    }
160}
161impl core::fmt::Debug for R {
162    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
163        f.debug_struct("BCR")
164            .field("cburstrw", &self.cburstrw())
165            .field("asyncwait", &self.asyncwait())
166            .field("extmod", &self.extmod())
167            .field("waiten", &self.waiten())
168            .field("wren", &self.wren())
169            .field("waitcfg", &self.waitcfg())
170            .field("waitpol", &self.waitpol())
171            .field("bursten", &self.bursten())
172            .field("faccen", &self.faccen())
173            .field("mwid", &self.mwid())
174            .field("mtyp", &self.mtyp())
175            .field("muxen", &self.muxen())
176            .field("mbken", &self.mbken())
177            .field("cpsize", &self.cpsize())
178            .finish()
179    }
180}
181impl W {
182    ///Bit 0 - MBKEN
183    #[inline(always)]
184    pub fn mbken(&mut self) -> MBKEN_W<BCRrs> {
185        MBKEN_W::new(self, 0)
186    }
187    ///Bit 1 - MUXEN
188    #[inline(always)]
189    pub fn muxen(&mut self) -> MUXEN_W<BCRrs> {
190        MUXEN_W::new(self, 1)
191    }
192    ///Bits 2:3 - MTYP
193    #[inline(always)]
194    pub fn mtyp(&mut self) -> MTYP_W<BCRrs> {
195        MTYP_W::new(self, 2)
196    }
197    ///Bits 4:5 - MWID
198    #[inline(always)]
199    pub fn mwid(&mut self) -> MWID_W<BCRrs> {
200        MWID_W::new(self, 4)
201    }
202    ///Bit 6 - FACCEN
203    #[inline(always)]
204    pub fn faccen(&mut self) -> FACCEN_W<BCRrs> {
205        FACCEN_W::new(self, 6)
206    }
207    ///Bit 8 - BURSTEN
208    #[inline(always)]
209    pub fn bursten(&mut self) -> BURSTEN_W<BCRrs> {
210        BURSTEN_W::new(self, 8)
211    }
212    ///Bit 9 - WAITPOL
213    #[inline(always)]
214    pub fn waitpol(&mut self) -> WAITPOL_W<BCRrs> {
215        WAITPOL_W::new(self, 9)
216    }
217    ///Bit 11 - WAITCFG
218    #[inline(always)]
219    pub fn waitcfg(&mut self) -> WAITCFG_W<BCRrs> {
220        WAITCFG_W::new(self, 11)
221    }
222    ///Bit 12 - WREN
223    #[inline(always)]
224    pub fn wren(&mut self) -> WREN_W<BCRrs> {
225        WREN_W::new(self, 12)
226    }
227    ///Bit 13 - WAITEN
228    #[inline(always)]
229    pub fn waiten(&mut self) -> WAITEN_W<BCRrs> {
230        WAITEN_W::new(self, 13)
231    }
232    ///Bit 14 - EXTMOD
233    #[inline(always)]
234    pub fn extmod(&mut self) -> EXTMOD_W<BCRrs> {
235        EXTMOD_W::new(self, 14)
236    }
237    ///Bit 15 - ASYNCWAIT
238    #[inline(always)]
239    pub fn asyncwait(&mut self) -> ASYNCWAIT_W<BCRrs> {
240        ASYNCWAIT_W::new(self, 15)
241    }
242    ///Bits 16:18 - CRAM page size
243    #[inline(always)]
244    pub fn cpsize(&mut self) -> CPSIZE_W<BCRrs> {
245        CPSIZE_W::new(self, 16)
246    }
247    ///Bit 19 - CBURSTRW
248    #[inline(always)]
249    pub fn cburstrw(&mut self) -> CBURSTRW_W<BCRrs> {
250        CBURSTRW_W::new(self, 19)
251    }
252}
253/**SRAM/NOR-Flash chip-select control register %s
254
255You can [`read`](crate::Reg::read) this register and get [`bcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
256
257See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#FMC:BCR[2])*/
258pub struct BCRrs;
259impl crate::RegisterSpec for BCRrs {
260    type Ux = u32;
261}
262///`read()` method returns [`bcr::R`](R) reader structure
263impl crate::Readable for BCRrs {}
264///`write(|w| ..)` method takes [`bcr::W`](W) writer structure
265impl crate::Writable for BCRrs {
266    type Safety = crate::Unsafe;
267}
268///`reset()` method sets BCR%s to value 0x30d0
269impl crate::Resettable for BCRrs {
270    const RESET_VALUE: u32 = 0x30d0;
271}
stm32l4/stm32l4x5/fmc/bcr.rs

stm32l4/stm32l4x5/fmc/
bcr.rs
