stm32l4/stm32l4x5/dma1/
ifcr.rs

1///Register `IFCR` writer
2pub type W = crate::W<IFCRrs>;
3/**Channel %s Global interrupt clear
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum CGIF1 {
9    ///1: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
10    Clear = 1,
11}
12impl From<CGIF1> for bool {
13    #[inline(always)]
14    fn from(variant: CGIF1) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `CGIF(1-7)` writer - Channel %s Global interrupt clear
19pub type CGIF_W<'a, REG> = crate::BitWriter<'a, REG, CGIF1>;
20impl<'a, REG> CGIF_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
25    #[inline(always)]
26    pub fn clear(self) -> &'a mut crate::W<REG> {
27        self.variant(CGIF1::Clear)
28    }
29}
30/**Channel %s Transfer Complete clear
31
32Value on reset: 0*/
33#[cfg_attr(feature = "defmt", derive(defmt::Format))]
34#[derive(Clone, Copy, Debug, PartialEq, Eq)]
35pub enum CTCIF1 {
36    ///1: Clears the TCIF flag in the ISR register
37    Clear = 1,
38}
39impl From<CTCIF1> for bool {
40    #[inline(always)]
41    fn from(variant: CTCIF1) -> Self {
42        variant as u8 != 0
43    }
44}
45///Field `CTCIF(1-7)` writer - Channel %s Transfer Complete clear
46pub type CTCIF_W<'a, REG> = crate::BitWriter<'a, REG, CTCIF1>;
47impl<'a, REG> CTCIF_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    ///Clears the TCIF flag in the ISR register
52    #[inline(always)]
53    pub fn clear(self) -> &'a mut crate::W<REG> {
54        self.variant(CTCIF1::Clear)
55    }
56}
57/**Channel %s Half Transfer clear
58
59Value on reset: 0*/
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum CHTIF1 {
63    ///1: Clears the HTIF flag in the ISR register
64    Clear = 1,
65}
66impl From<CHTIF1> for bool {
67    #[inline(always)]
68    fn from(variant: CHTIF1) -> Self {
69        variant as u8 != 0
70    }
71}
72///Field `CHTIF(1-7)` writer - Channel %s Half Transfer clear
73pub type CHTIF_W<'a, REG> = crate::BitWriter<'a, REG, CHTIF1>;
74impl<'a, REG> CHTIF_W<'a, REG>
75where
76    REG: crate::Writable + crate::RegisterSpec,
77{
78    ///Clears the HTIF flag in the ISR register
79    #[inline(always)]
80    pub fn clear(self) -> &'a mut crate::W<REG> {
81        self.variant(CHTIF1::Clear)
82    }
83}
84/**Channel %s Transfer Error clear
85
86Value on reset: 0*/
87#[cfg_attr(feature = "defmt", derive(defmt::Format))]
88#[derive(Clone, Copy, Debug, PartialEq, Eq)]
89pub enum CTEIF1 {
90    ///1: Clears the TEIF flag in the ISR register
91    Clear = 1,
92}
93impl From<CTEIF1> for bool {
94    #[inline(always)]
95    fn from(variant: CTEIF1) -> Self {
96        variant as u8 != 0
97    }
98}
99///Field `CTEIF(1-7)` writer - Channel %s Transfer Error clear
100pub type CTEIF_W<'a, REG> = crate::BitWriter<'a, REG, CTEIF1>;
101impl<'a, REG> CTEIF_W<'a, REG>
102where
103    REG: crate::Writable + crate::RegisterSpec,
104{
105    ///Clears the TEIF flag in the ISR register
106    #[inline(always)]
107    pub fn clear(self) -> &'a mut crate::W<REG> {
108        self.variant(CTEIF1::Clear)
109    }
110}
111impl core::fmt::Debug for crate::generic::Reg<IFCRrs> {
112    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
113        write!(f, "(not readable)")
114    }
115}
116impl W {
117    ///Channel (1-7) Global interrupt clear
118    ///
119    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CGIF1` field.</div>
120    #[inline(always)]
121    pub fn cgif(&mut self, n: u8) -> CGIF_W<IFCRrs> {
122        #[allow(clippy::no_effect)]
123        [(); 7][n as usize];
124        CGIF_W::new(self, n * 4)
125    }
126    ///Bit 0 - Channel 1 Global interrupt clear
127    #[inline(always)]
128    pub fn cgif1(&mut self) -> CGIF_W<IFCRrs> {
129        CGIF_W::new(self, 0)
130    }
131    ///Bit 4 - Channel 2 Global interrupt clear
132    #[inline(always)]
133    pub fn cgif2(&mut self) -> CGIF_W<IFCRrs> {
134        CGIF_W::new(self, 4)
135    }
136    ///Bit 8 - Channel 3 Global interrupt clear
137    #[inline(always)]
138    pub fn cgif3(&mut self) -> CGIF_W<IFCRrs> {
139        CGIF_W::new(self, 8)
140    }
141    ///Bit 12 - Channel 4 Global interrupt clear
142    #[inline(always)]
143    pub fn cgif4(&mut self) -> CGIF_W<IFCRrs> {
144        CGIF_W::new(self, 12)
145    }
146    ///Bit 16 - Channel 5 Global interrupt clear
147    #[inline(always)]
148    pub fn cgif5(&mut self) -> CGIF_W<IFCRrs> {
149        CGIF_W::new(self, 16)
150    }
151    ///Bit 20 - Channel 6 Global interrupt clear
152    #[inline(always)]
153    pub fn cgif6(&mut self) -> CGIF_W<IFCRrs> {
154        CGIF_W::new(self, 20)
155    }
156    ///Bit 24 - Channel 7 Global interrupt clear
157    #[inline(always)]
158    pub fn cgif7(&mut self) -> CGIF_W<IFCRrs> {
159        CGIF_W::new(self, 24)
160    }
161    ///Channel (1-7) Transfer Complete clear
162    ///
163    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CTCIF1` field.</div>
164    #[inline(always)]
165    pub fn ctcif(&mut self, n: u8) -> CTCIF_W<IFCRrs> {
166        #[allow(clippy::no_effect)]
167        [(); 7][n as usize];
168        CTCIF_W::new(self, n * 4 + 1)
169    }
170    ///Bit 1 - Channel 1 Transfer Complete clear
171    #[inline(always)]
172    pub fn ctcif1(&mut self) -> CTCIF_W<IFCRrs> {
173        CTCIF_W::new(self, 1)
174    }
175    ///Bit 5 - Channel 2 Transfer Complete clear
176    #[inline(always)]
177    pub fn ctcif2(&mut self) -> CTCIF_W<IFCRrs> {
178        CTCIF_W::new(self, 5)
179    }
180    ///Bit 9 - Channel 3 Transfer Complete clear
181    #[inline(always)]
182    pub fn ctcif3(&mut self) -> CTCIF_W<IFCRrs> {
183        CTCIF_W::new(self, 9)
184    }
185    ///Bit 13 - Channel 4 Transfer Complete clear
186    #[inline(always)]
187    pub fn ctcif4(&mut self) -> CTCIF_W<IFCRrs> {
188        CTCIF_W::new(self, 13)
189    }
190    ///Bit 17 - Channel 5 Transfer Complete clear
191    #[inline(always)]
192    pub fn ctcif5(&mut self) -> CTCIF_W<IFCRrs> {
193        CTCIF_W::new(self, 17)
194    }
195    ///Bit 21 - Channel 6 Transfer Complete clear
196    #[inline(always)]
197    pub fn ctcif6(&mut self) -> CTCIF_W<IFCRrs> {
198        CTCIF_W::new(self, 21)
199    }
200    ///Bit 25 - Channel 7 Transfer Complete clear
201    #[inline(always)]
202    pub fn ctcif7(&mut self) -> CTCIF_W<IFCRrs> {
203        CTCIF_W::new(self, 25)
204    }
205    ///Channel (1-7) Half Transfer clear
206    ///
207    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CHTIF1` field.</div>
208    #[inline(always)]
209    pub fn chtif(&mut self, n: u8) -> CHTIF_W<IFCRrs> {
210        #[allow(clippy::no_effect)]
211        [(); 7][n as usize];
212        CHTIF_W::new(self, n * 4 + 2)
213    }
214    ///Bit 2 - Channel 1 Half Transfer clear
215    #[inline(always)]
216    pub fn chtif1(&mut self) -> CHTIF_W<IFCRrs> {
217        CHTIF_W::new(self, 2)
218    }
219    ///Bit 6 - Channel 2 Half Transfer clear
220    #[inline(always)]
221    pub fn chtif2(&mut self) -> CHTIF_W<IFCRrs> {
222        CHTIF_W::new(self, 6)
223    }
224    ///Bit 10 - Channel 3 Half Transfer clear
225    #[inline(always)]
226    pub fn chtif3(&mut self) -> CHTIF_W<IFCRrs> {
227        CHTIF_W::new(self, 10)
228    }
229    ///Bit 14 - Channel 4 Half Transfer clear
230    #[inline(always)]
231    pub fn chtif4(&mut self) -> CHTIF_W<IFCRrs> {
232        CHTIF_W::new(self, 14)
233    }
234    ///Bit 18 - Channel 5 Half Transfer clear
235    #[inline(always)]
236    pub fn chtif5(&mut self) -> CHTIF_W<IFCRrs> {
237        CHTIF_W::new(self, 18)
238    }
239    ///Bit 22 - Channel 6 Half Transfer clear
240    #[inline(always)]
241    pub fn chtif6(&mut self) -> CHTIF_W<IFCRrs> {
242        CHTIF_W::new(self, 22)
243    }
244    ///Bit 26 - Channel 7 Half Transfer clear
245    #[inline(always)]
246    pub fn chtif7(&mut self) -> CHTIF_W<IFCRrs> {
247        CHTIF_W::new(self, 26)
248    }
249    ///Channel (1-7) Transfer Error clear
250    ///
251    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CTEIF1` field.</div>
252    #[inline(always)]
253    pub fn cteif(&mut self, n: u8) -> CTEIF_W<IFCRrs> {
254        #[allow(clippy::no_effect)]
255        [(); 7][n as usize];
256        CTEIF_W::new(self, n * 4 + 3)
257    }
258    ///Bit 3 - Channel 1 Transfer Error clear
259    #[inline(always)]
260    pub fn cteif1(&mut self) -> CTEIF_W<IFCRrs> {
261        CTEIF_W::new(self, 3)
262    }
263    ///Bit 7 - Channel 2 Transfer Error clear
264    #[inline(always)]
265    pub fn cteif2(&mut self) -> CTEIF_W<IFCRrs> {
266        CTEIF_W::new(self, 7)
267    }
268    ///Bit 11 - Channel 3 Transfer Error clear
269    #[inline(always)]
270    pub fn cteif3(&mut self) -> CTEIF_W<IFCRrs> {
271        CTEIF_W::new(self, 11)
272    }
273    ///Bit 15 - Channel 4 Transfer Error clear
274    #[inline(always)]
275    pub fn cteif4(&mut self) -> CTEIF_W<IFCRrs> {
276        CTEIF_W::new(self, 15)
277    }
278    ///Bit 19 - Channel 5 Transfer Error clear
279    #[inline(always)]
280    pub fn cteif5(&mut self) -> CTEIF_W<IFCRrs> {
281        CTEIF_W::new(self, 19)
282    }
283    ///Bit 23 - Channel 6 Transfer Error clear
284    #[inline(always)]
285    pub fn cteif6(&mut self) -> CTEIF_W<IFCRrs> {
286        CTEIF_W::new(self, 23)
287    }
288    ///Bit 27 - Channel 7 Transfer Error clear
289    #[inline(always)]
290    pub fn cteif7(&mut self) -> CTEIF_W<IFCRrs> {
291        CTEIF_W::new(self, 27)
292    }
293}
294/**interrupt flag clear register
295
296You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
297
298See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#DMA1:IFCR)*/
299pub struct IFCRrs;
300impl crate::RegisterSpec for IFCRrs {
301    type Ux = u32;
302}
303///`write(|w| ..)` method takes [`ifcr::W`](W) writer structure
304impl crate::Writable for IFCRrs {
305    type Safety = crate::Unsafe;
306}
307///`reset()` method sets IFCR to value 0
308impl crate::Resettable for IFCRrs {}
stm32l4/stm32l4x5/dma1/ifcr.rs

stm32l4/stm32l4x5/dma1/
ifcr.rs
