stm32l4/stm32l4x5/dfsdm/ch/
cfgr1.rs

1///Register `CFGR1` reader
2pub type R = crate::R<CFGR1rs>;
3///Register `CFGR1` writer
4pub type W = crate::W<CFGR1rs>;
5/**SITP
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum SITP {
12    ///0: SPI with rising edge to strobe data
13    SpirisingEdge = 0,
14    ///1: SPI with falling edge to strobe data
15    SpifallingEdge = 1,
16    ///2: Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
17    Manchester = 2,
18    ///3: Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0
19    ManchesterInverted = 3,
20}
21impl From<SITP> for u8 {
22    #[inline(always)]
23    fn from(variant: SITP) -> Self {
24        variant as _
25    }
26}
27impl crate::FieldSpec for SITP {
28    type Ux = u8;
29}
30impl crate::IsEnum for SITP {}
31///Field `SITP` reader - SITP
32pub type SITP_R = crate::FieldReader<SITP>;
33impl SITP_R {
34    ///Get enumerated values variant
35    #[inline(always)]
36    pub const fn variant(&self) -> SITP {
37        match self.bits {
38            0 => SITP::SpirisingEdge,
39            1 => SITP::SpifallingEdge,
40            2 => SITP::Manchester,
41            3 => SITP::ManchesterInverted,
42            _ => unreachable!(),
43        }
44    }
45    ///SPI with rising edge to strobe data
46    #[inline(always)]
47    pub fn is_spirising_edge(&self) -> bool {
48        *self == SITP::SpirisingEdge
49    }
50    ///SPI with falling edge to strobe data
51    #[inline(always)]
52    pub fn is_spifalling_edge(&self) -> bool {
53        *self == SITP::SpifallingEdge
54    }
55    ///Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
56    #[inline(always)]
57    pub fn is_manchester(&self) -> bool {
58        *self == SITP::Manchester
59    }
60    ///Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0
61    #[inline(always)]
62    pub fn is_manchester_inverted(&self) -> bool {
63        *self == SITP::ManchesterInverted
64    }
65}
66///Field `SITP` writer - SITP
67pub type SITP_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SITP, crate::Safe>;
68impl<'a, REG> SITP_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    ///SPI with rising edge to strobe data
74    #[inline(always)]
75    pub fn spirising_edge(self) -> &'a mut crate::W<REG> {
76        self.variant(SITP::SpirisingEdge)
77    }
78    ///SPI with falling edge to strobe data
79    #[inline(always)]
80    pub fn spifalling_edge(self) -> &'a mut crate::W<REG> {
81        self.variant(SITP::SpifallingEdge)
82    }
83    ///Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
84    #[inline(always)]
85    pub fn manchester(self) -> &'a mut crate::W<REG> {
86        self.variant(SITP::Manchester)
87    }
88    ///Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0
89    #[inline(always)]
90    pub fn manchester_inverted(self) -> &'a mut crate::W<REG> {
91        self.variant(SITP::ManchesterInverted)
92    }
93}
94/**SPICKSEL
95
96Value on reset: 0*/
97#[cfg_attr(feature = "defmt", derive(defmt::Format))]
98#[derive(Clone, Copy, Debug, PartialEq, Eq)]
99#[repr(u8)]
100pub enum SPICKSEL {
101    ///0: Clock coming from external CKINy input - sampling point according SITP\[1:0\]
102    Ckin = 0,
103    ///1: Clock coming from internal CKOUT output - sampling point according SITP\[1:0\]
104    Ckout = 1,
105    ///2: Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge)
106    CkoutsecondFalling = 2,
107    ///3: Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge)
108    CkoutsecondRising = 3,
109}
110impl From<SPICKSEL> for u8 {
111    #[inline(always)]
112    fn from(variant: SPICKSEL) -> Self {
113        variant as _
114    }
115}
116impl crate::FieldSpec for SPICKSEL {
117    type Ux = u8;
118}
119impl crate::IsEnum for SPICKSEL {}
120///Field `SPICKSEL` reader - SPICKSEL
121pub type SPICKSEL_R = crate::FieldReader<SPICKSEL>;
122impl SPICKSEL_R {
123    ///Get enumerated values variant
124    #[inline(always)]
125    pub const fn variant(&self) -> SPICKSEL {
126        match self.bits {
127            0 => SPICKSEL::Ckin,
128            1 => SPICKSEL::Ckout,
129            2 => SPICKSEL::CkoutsecondFalling,
130            3 => SPICKSEL::CkoutsecondRising,
131            _ => unreachable!(),
132        }
133    }
134    ///Clock coming from external CKINy input - sampling point according SITP\[1:0\]
135    #[inline(always)]
136    pub fn is_ckin(&self) -> bool {
137        *self == SPICKSEL::Ckin
138    }
139    ///Clock coming from internal CKOUT output - sampling point according SITP\[1:0\]
140    #[inline(always)]
141    pub fn is_ckout(&self) -> bool {
142        *self == SPICKSEL::Ckout
143    }
144    ///Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge)
145    #[inline(always)]
146    pub fn is_ckoutsecond_falling(&self) -> bool {
147        *self == SPICKSEL::CkoutsecondFalling
148    }
149    ///Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge)
150    #[inline(always)]
151    pub fn is_ckoutsecond_rising(&self) -> bool {
152        *self == SPICKSEL::CkoutsecondRising
153    }
154}
155///Field `SPICKSEL` writer - SPICKSEL
156pub type SPICKSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SPICKSEL, crate::Safe>;
157impl<'a, REG> SPICKSEL_W<'a, REG>
158where
159    REG: crate::Writable + crate::RegisterSpec,
160    REG::Ux: From<u8>,
161{
162    ///Clock coming from external CKINy input - sampling point according SITP\[1:0\]
163    #[inline(always)]
164    pub fn ckin(self) -> &'a mut crate::W<REG> {
165        self.variant(SPICKSEL::Ckin)
166    }
167    ///Clock coming from internal CKOUT output - sampling point according SITP\[1:0\]
168    #[inline(always)]
169    pub fn ckout(self) -> &'a mut crate::W<REG> {
170        self.variant(SPICKSEL::Ckout)
171    }
172    ///Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge)
173    #[inline(always)]
174    pub fn ckoutsecond_falling(self) -> &'a mut crate::W<REG> {
175        self.variant(SPICKSEL::CkoutsecondFalling)
176    }
177    ///Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge)
178    #[inline(always)]
179    pub fn ckoutsecond_rising(self) -> &'a mut crate::W<REG> {
180        self.variant(SPICKSEL::CkoutsecondRising)
181    }
182}
183/**SCDEN
184
185Value on reset: 0*/
186#[cfg_attr(feature = "defmt", derive(defmt::Format))]
187#[derive(Clone, Copy, Debug, PartialEq, Eq)]
188pub enum SCDEN {
189    ///0: Input channel y will not be guarded by the short-circuit detector
190    Disabled = 0,
191    ///1: Input channel y will be continuously guarded by the short-circuit detector
192    Enabled = 1,
193}
194impl From<SCDEN> for bool {
195    #[inline(always)]
196    fn from(variant: SCDEN) -> Self {
197        variant as u8 != 0
198    }
199}
200///Field `SCDEN` reader - SCDEN
201pub type SCDEN_R = crate::BitReader<SCDEN>;
202impl SCDEN_R {
203    ///Get enumerated values variant
204    #[inline(always)]
205    pub const fn variant(&self) -> SCDEN {
206        match self.bits {
207            false => SCDEN::Disabled,
208            true => SCDEN::Enabled,
209        }
210    }
211    ///Input channel y will not be guarded by the short-circuit detector
212    #[inline(always)]
213    pub fn is_disabled(&self) -> bool {
214        *self == SCDEN::Disabled
215    }
216    ///Input channel y will be continuously guarded by the short-circuit detector
217    #[inline(always)]
218    pub fn is_enabled(&self) -> bool {
219        *self == SCDEN::Enabled
220    }
221}
222///Field `SCDEN` writer - SCDEN
223pub type SCDEN_W<'a, REG> = crate::BitWriter<'a, REG, SCDEN>;
224impl<'a, REG> SCDEN_W<'a, REG>
225where
226    REG: crate::Writable + crate::RegisterSpec,
227{
228    ///Input channel y will not be guarded by the short-circuit detector
229    #[inline(always)]
230    pub fn disabled(self) -> &'a mut crate::W<REG> {
231        self.variant(SCDEN::Disabled)
232    }
233    ///Input channel y will be continuously guarded by the short-circuit detector
234    #[inline(always)]
235    pub fn enabled(self) -> &'a mut crate::W<REG> {
236        self.variant(SCDEN::Enabled)
237    }
238}
239/**CKABEN
240
241Value on reset: 0*/
242#[cfg_attr(feature = "defmt", derive(defmt::Format))]
243#[derive(Clone, Copy, Debug, PartialEq, Eq)]
244pub enum CKABEN {
245    ///0: Clock absence detector disabled on channel y
246    Disabled = 0,
247    ///1: Clock absence detector enabled on channel y
248    Enabled = 1,
249}
250impl From<CKABEN> for bool {
251    #[inline(always)]
252    fn from(variant: CKABEN) -> Self {
253        variant as u8 != 0
254    }
255}
256///Field `CKABEN` reader - CKABEN
257pub type CKABEN_R = crate::BitReader<CKABEN>;
258impl CKABEN_R {
259    ///Get enumerated values variant
260    #[inline(always)]
261    pub const fn variant(&self) -> CKABEN {
262        match self.bits {
263            false => CKABEN::Disabled,
264            true => CKABEN::Enabled,
265        }
266    }
267    ///Clock absence detector disabled on channel y
268    #[inline(always)]
269    pub fn is_disabled(&self) -> bool {
270        *self == CKABEN::Disabled
271    }
272    ///Clock absence detector enabled on channel y
273    #[inline(always)]
274    pub fn is_enabled(&self) -> bool {
275        *self == CKABEN::Enabled
276    }
277}
278///Field `CKABEN` writer - CKABEN
279pub type CKABEN_W<'a, REG> = crate::BitWriter<'a, REG, CKABEN>;
280impl<'a, REG> CKABEN_W<'a, REG>
281where
282    REG: crate::Writable + crate::RegisterSpec,
283{
284    ///Clock absence detector disabled on channel y
285    #[inline(always)]
286    pub fn disabled(self) -> &'a mut crate::W<REG> {
287        self.variant(CKABEN::Disabled)
288    }
289    ///Clock absence detector enabled on channel y
290    #[inline(always)]
291    pub fn enabled(self) -> &'a mut crate::W<REG> {
292        self.variant(CKABEN::Enabled)
293    }
294}
295/**CHEN
296
297Value on reset: 0*/
298#[cfg_attr(feature = "defmt", derive(defmt::Format))]
299#[derive(Clone, Copy, Debug, PartialEq, Eq)]
300pub enum CHEN {
301    ///0: Channel y disabled
302    Disabled = 0,
303    ///1: Channel y enabled
304    Enabled = 1,
305}
306impl From<CHEN> for bool {
307    #[inline(always)]
308    fn from(variant: CHEN) -> Self {
309        variant as u8 != 0
310    }
311}
312///Field `CHEN` reader - CHEN
313pub type CHEN_R = crate::BitReader<CHEN>;
314impl CHEN_R {
315    ///Get enumerated values variant
316    #[inline(always)]
317    pub const fn variant(&self) -> CHEN {
318        match self.bits {
319            false => CHEN::Disabled,
320            true => CHEN::Enabled,
321        }
322    }
323    ///Channel y disabled
324    #[inline(always)]
325    pub fn is_disabled(&self) -> bool {
326        *self == CHEN::Disabled
327    }
328    ///Channel y enabled
329    #[inline(always)]
330    pub fn is_enabled(&self) -> bool {
331        *self == CHEN::Enabled
332    }
333}
334///Field `CHEN` writer - CHEN
335pub type CHEN_W<'a, REG> = crate::BitWriter<'a, REG, CHEN>;
336impl<'a, REG> CHEN_W<'a, REG>
337where
338    REG: crate::Writable + crate::RegisterSpec,
339{
340    ///Channel y disabled
341    #[inline(always)]
342    pub fn disabled(self) -> &'a mut crate::W<REG> {
343        self.variant(CHEN::Disabled)
344    }
345    ///Channel y enabled
346    #[inline(always)]
347    pub fn enabled(self) -> &'a mut crate::W<REG> {
348        self.variant(CHEN::Enabled)
349    }
350}
351/**CHINSEL
352
353Value on reset: 0*/
354#[cfg_attr(feature = "defmt", derive(defmt::Format))]
355#[derive(Clone, Copy, Debug, PartialEq, Eq)]
356pub enum CHINSEL {
357    ///0: Channel inputs are taken from pins of the same channel y
358    SameChannel = 0,
359    ///1: Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8)
360    FollowingChannel = 1,
361}
362impl From<CHINSEL> for bool {
363    #[inline(always)]
364    fn from(variant: CHINSEL) -> Self {
365        variant as u8 != 0
366    }
367}
368///Field `CHINSEL` reader - CHINSEL
369pub type CHINSEL_R = crate::BitReader<CHINSEL>;
370impl CHINSEL_R {
371    ///Get enumerated values variant
372    #[inline(always)]
373    pub const fn variant(&self) -> CHINSEL {
374        match self.bits {
375            false => CHINSEL::SameChannel,
376            true => CHINSEL::FollowingChannel,
377        }
378    }
379    ///Channel inputs are taken from pins of the same channel y
380    #[inline(always)]
381    pub fn is_same_channel(&self) -> bool {
382        *self == CHINSEL::SameChannel
383    }
384    ///Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8)
385    #[inline(always)]
386    pub fn is_following_channel(&self) -> bool {
387        *self == CHINSEL::FollowingChannel
388    }
389}
390///Field `CHINSEL` writer - CHINSEL
391pub type CHINSEL_W<'a, REG> = crate::BitWriter<'a, REG, CHINSEL>;
392impl<'a, REG> CHINSEL_W<'a, REG>
393where
394    REG: crate::Writable + crate::RegisterSpec,
395{
396    ///Channel inputs are taken from pins of the same channel y
397    #[inline(always)]
398    pub fn same_channel(self) -> &'a mut crate::W<REG> {
399        self.variant(CHINSEL::SameChannel)
400    }
401    ///Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8)
402    #[inline(always)]
403    pub fn following_channel(self) -> &'a mut crate::W<REG> {
404        self.variant(CHINSEL::FollowingChannel)
405    }
406}
407/**DATMPX
408
409Value on reset: 0*/
410#[cfg_attr(feature = "defmt", derive(defmt::Format))]
411#[derive(Clone, Copy, Debug, PartialEq, Eq)]
412#[repr(u8)]
413pub enum DATMPX {
414    ///0: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected
415    External = 0,
416    ///1: Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0\[15:0\] part of DFSDM_CHyDATINR register
417    Adc = 1,
418    ///2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK\[1:0\] bit field setting
419    Internal = 2,
420}
421impl From<DATMPX> for u8 {
422    #[inline(always)]
423    fn from(variant: DATMPX) -> Self {
424        variant as _
425    }
426}
427impl crate::FieldSpec for DATMPX {
428    type Ux = u8;
429}
430impl crate::IsEnum for DATMPX {}
431///Field `DATMPX` reader - DATMPX
432pub type DATMPX_R = crate::FieldReader<DATMPX>;
433impl DATMPX_R {
434    ///Get enumerated values variant
435    #[inline(always)]
436    pub const fn variant(&self) -> Option<DATMPX> {
437        match self.bits {
438            0 => Some(DATMPX::External),
439            1 => Some(DATMPX::Adc),
440            2 => Some(DATMPX::Internal),
441            _ => None,
442        }
443    }
444    ///Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected
445    #[inline(always)]
446    pub fn is_external(&self) -> bool {
447        *self == DATMPX::External
448    }
449    ///Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0\[15:0\] part of DFSDM_CHyDATINR register
450    #[inline(always)]
451    pub fn is_adc(&self) -> bool {
452        *self == DATMPX::Adc
453    }
454    ///Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK\[1:0\] bit field setting
455    #[inline(always)]
456    pub fn is_internal(&self) -> bool {
457        *self == DATMPX::Internal
458    }
459}
460///Field `DATMPX` writer - DATMPX
461pub type DATMPX_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DATMPX>;
462impl<'a, REG> DATMPX_W<'a, REG>
463where
464    REG: crate::Writable + crate::RegisterSpec,
465    REG::Ux: From<u8>,
466{
467    ///Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected
468    #[inline(always)]
469    pub fn external(self) -> &'a mut crate::W<REG> {
470        self.variant(DATMPX::External)
471    }
472    ///Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0\[15:0\] part of DFSDM_CHyDATINR register
473    #[inline(always)]
474    pub fn adc(self) -> &'a mut crate::W<REG> {
475        self.variant(DATMPX::Adc)
476    }
477    ///Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK\[1:0\] bit field setting
478    #[inline(always)]
479    pub fn internal(self) -> &'a mut crate::W<REG> {
480        self.variant(DATMPX::Internal)
481    }
482}
483/**DATPACK
484
485Value on reset: 0*/
486#[cfg_attr(feature = "defmt", derive(defmt::Format))]
487#[derive(Clone, Copy, Debug, PartialEq, Eq)]
488#[repr(u8)]
489pub enum DATPACK {
490    ///0: Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0\[15:0\]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y
491    Standard = 0,
492    ///1: : Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0\[15:0\] (assigned to channel y) –second sample INDAT1\[15:0\] (assigned to channel y)
493    Interleaved = 1,
494    ///2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0\[15:0\] (assigned to channel y) –second sample INDAT1\[15:0\] (assigned to channel y+1)
495    Dual = 2,
496}
497impl From<DATPACK> for u8 {
498    #[inline(always)]
499    fn from(variant: DATPACK) -> Self {
500        variant as _
501    }
502}
503impl crate::FieldSpec for DATPACK {
504    type Ux = u8;
505}
506impl crate::IsEnum for DATPACK {}
507///Field `DATPACK` reader - DATPACK
508pub type DATPACK_R = crate::FieldReader<DATPACK>;
509impl DATPACK_R {
510    ///Get enumerated values variant
511    #[inline(always)]
512    pub const fn variant(&self) -> Option<DATPACK> {
513        match self.bits {
514            0 => Some(DATPACK::Standard),
515            1 => Some(DATPACK::Interleaved),
516            2 => Some(DATPACK::Dual),
517            _ => None,
518        }
519    }
520    ///Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0\[15:0\]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y
521    #[inline(always)]
522    pub fn is_standard(&self) -> bool {
523        *self == DATPACK::Standard
524    }
525    ///: Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0\[15:0\] (assigned to channel y) –second sample INDAT1\[15:0\] (assigned to channel y)
526    #[inline(always)]
527    pub fn is_interleaved(&self) -> bool {
528        *self == DATPACK::Interleaved
529    }
530    ///Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0\[15:0\] (assigned to channel y) –second sample INDAT1\[15:0\] (assigned to channel y+1)
531    #[inline(always)]
532    pub fn is_dual(&self) -> bool {
533        *self == DATPACK::Dual
534    }
535}
536///Field `DATPACK` writer - DATPACK
537pub type DATPACK_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DATPACK>;
538impl<'a, REG> DATPACK_W<'a, REG>
539where
540    REG: crate::Writable + crate::RegisterSpec,
541    REG::Ux: From<u8>,
542{
543    ///Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0\[15:0\]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y
544    #[inline(always)]
545    pub fn standard(self) -> &'a mut crate::W<REG> {
546        self.variant(DATPACK::Standard)
547    }
548    ///: Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0\[15:0\] (assigned to channel y) –second sample INDAT1\[15:0\] (assigned to channel y)
549    #[inline(always)]
550    pub fn interleaved(self) -> &'a mut crate::W<REG> {
551        self.variant(DATPACK::Interleaved)
552    }
553    ///Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0\[15:0\] (assigned to channel y) –second sample INDAT1\[15:0\] (assigned to channel y+1)
554    #[inline(always)]
555    pub fn dual(self) -> &'a mut crate::W<REG> {
556        self.variant(DATPACK::Dual)
557    }
558}
559///Field `CKOUTDIV` reader - CKOUTDIV
560pub type CKOUTDIV_R = crate::FieldReader;
561///Field `CKOUTDIV` writer - CKOUTDIV
562pub type CKOUTDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8, u8, crate::Safe>;
563/**CKOUTSRC
564
565Value on reset: 0*/
566#[cfg_attr(feature = "defmt", derive(defmt::Format))]
567#[derive(Clone, Copy, Debug, PartialEq, Eq)]
568pub enum CKOUTSRC {
569    ///0: Source for output clock is from system clock
570    Sysclk = 0,
571    ///1: Source for output clock is from audio clock
572    Audclk = 1,
573}
574impl From<CKOUTSRC> for bool {
575    #[inline(always)]
576    fn from(variant: CKOUTSRC) -> Self {
577        variant as u8 != 0
578    }
579}
580///Field `CKOUTSRC` reader - CKOUTSRC
581pub type CKOUTSRC_R = crate::BitReader<CKOUTSRC>;
582impl CKOUTSRC_R {
583    ///Get enumerated values variant
584    #[inline(always)]
585    pub const fn variant(&self) -> CKOUTSRC {
586        match self.bits {
587            false => CKOUTSRC::Sysclk,
588            true => CKOUTSRC::Audclk,
589        }
590    }
591    ///Source for output clock is from system clock
592    #[inline(always)]
593    pub fn is_sysclk(&self) -> bool {
594        *self == CKOUTSRC::Sysclk
595    }
596    ///Source for output clock is from audio clock
597    #[inline(always)]
598    pub fn is_audclk(&self) -> bool {
599        *self == CKOUTSRC::Audclk
600    }
601}
602///Field `CKOUTSRC` writer - CKOUTSRC
603pub type CKOUTSRC_W<'a, REG> = crate::BitWriter<'a, REG, CKOUTSRC>;
604impl<'a, REG> CKOUTSRC_W<'a, REG>
605where
606    REG: crate::Writable + crate::RegisterSpec,
607{
608    ///Source for output clock is from system clock
609    #[inline(always)]
610    pub fn sysclk(self) -> &'a mut crate::W<REG> {
611        self.variant(CKOUTSRC::Sysclk)
612    }
613    ///Source for output clock is from audio clock
614    #[inline(always)]
615    pub fn audclk(self) -> &'a mut crate::W<REG> {
616        self.variant(CKOUTSRC::Audclk)
617    }
618}
619/**DFSDMEN
620
621Value on reset: 0*/
622#[cfg_attr(feature = "defmt", derive(defmt::Format))]
623#[derive(Clone, Copy, Debug, PartialEq, Eq)]
624pub enum DFSDMEN {
625    ///0: DFSDM interface disabled
626    Disabled = 0,
627    ///1: DFSDM interface enabled
628    Enabled = 1,
629}
630impl From<DFSDMEN> for bool {
631    #[inline(always)]
632    fn from(variant: DFSDMEN) -> Self {
633        variant as u8 != 0
634    }
635}
636///Field `DFSDMEN` reader - DFSDMEN
637pub type DFSDMEN_R = crate::BitReader<DFSDMEN>;
638impl DFSDMEN_R {
639    ///Get enumerated values variant
640    #[inline(always)]
641    pub const fn variant(&self) -> DFSDMEN {
642        match self.bits {
643            false => DFSDMEN::Disabled,
644            true => DFSDMEN::Enabled,
645        }
646    }
647    ///DFSDM interface disabled
648    #[inline(always)]
649    pub fn is_disabled(&self) -> bool {
650        *self == DFSDMEN::Disabled
651    }
652    ///DFSDM interface enabled
653    #[inline(always)]
654    pub fn is_enabled(&self) -> bool {
655        *self == DFSDMEN::Enabled
656    }
657}
658///Field `DFSDMEN` writer - DFSDMEN
659pub type DFSDMEN_W<'a, REG> = crate::BitWriter<'a, REG, DFSDMEN>;
660impl<'a, REG> DFSDMEN_W<'a, REG>
661where
662    REG: crate::Writable + crate::RegisterSpec,
663{
664    ///DFSDM interface disabled
665    #[inline(always)]
666    pub fn disabled(self) -> &'a mut crate::W<REG> {
667        self.variant(DFSDMEN::Disabled)
668    }
669    ///DFSDM interface enabled
670    #[inline(always)]
671    pub fn enabled(self) -> &'a mut crate::W<REG> {
672        self.variant(DFSDMEN::Enabled)
673    }
674}
675impl R {
676    ///Bits 0:1 - SITP
677    #[inline(always)]
678    pub fn sitp(&self) -> SITP_R {
679        SITP_R::new((self.bits & 3) as u8)
680    }
681    ///Bits 2:3 - SPICKSEL
682    #[inline(always)]
683    pub fn spicksel(&self) -> SPICKSEL_R {
684        SPICKSEL_R::new(((self.bits >> 2) & 3) as u8)
685    }
686    ///Bit 5 - SCDEN
687    #[inline(always)]
688    pub fn scden(&self) -> SCDEN_R {
689        SCDEN_R::new(((self.bits >> 5) & 1) != 0)
690    }
691    ///Bit 6 - CKABEN
692    #[inline(always)]
693    pub fn ckaben(&self) -> CKABEN_R {
694        CKABEN_R::new(((self.bits >> 6) & 1) != 0)
695    }
696    ///Bit 7 - CHEN
697    #[inline(always)]
698    pub fn chen(&self) -> CHEN_R {
699        CHEN_R::new(((self.bits >> 7) & 1) != 0)
700    }
701    ///Bit 8 - CHINSEL
702    #[inline(always)]
703    pub fn chinsel(&self) -> CHINSEL_R {
704        CHINSEL_R::new(((self.bits >> 8) & 1) != 0)
705    }
706    ///Bits 12:13 - DATMPX
707    #[inline(always)]
708    pub fn datmpx(&self) -> DATMPX_R {
709        DATMPX_R::new(((self.bits >> 12) & 3) as u8)
710    }
711    ///Bits 14:15 - DATPACK
712    #[inline(always)]
713    pub fn datpack(&self) -> DATPACK_R {
714        DATPACK_R::new(((self.bits >> 14) & 3) as u8)
715    }
716    ///Bits 16:23 - CKOUTDIV
717    #[inline(always)]
718    pub fn ckoutdiv(&self) -> CKOUTDIV_R {
719        CKOUTDIV_R::new(((self.bits >> 16) & 0xff) as u8)
720    }
721    ///Bit 30 - CKOUTSRC
722    #[inline(always)]
723    pub fn ckoutsrc(&self) -> CKOUTSRC_R {
724        CKOUTSRC_R::new(((self.bits >> 30) & 1) != 0)
725    }
726    ///Bit 31 - DFSDMEN
727    #[inline(always)]
728    pub fn dfsdmen(&self) -> DFSDMEN_R {
729        DFSDMEN_R::new(((self.bits >> 31) & 1) != 0)
730    }
731}
732impl core::fmt::Debug for R {
733    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
734        f.debug_struct("CFGR1")
735            .field("dfsdmen", &self.dfsdmen())
736            .field("ckoutsrc", &self.ckoutsrc())
737            .field("ckoutdiv", &self.ckoutdiv())
738            .field("datpack", &self.datpack())
739            .field("datmpx", &self.datmpx())
740            .field("chinsel", &self.chinsel())
741            .field("chen", &self.chen())
742            .field("ckaben", &self.ckaben())
743            .field("scden", &self.scden())
744            .field("spicksel", &self.spicksel())
745            .field("sitp", &self.sitp())
746            .finish()
747    }
748}
749impl W {
750    ///Bits 0:1 - SITP
751    #[inline(always)]
752    pub fn sitp(&mut self) -> SITP_W<CFGR1rs> {
753        SITP_W::new(self, 0)
754    }
755    ///Bits 2:3 - SPICKSEL
756    #[inline(always)]
757    pub fn spicksel(&mut self) -> SPICKSEL_W<CFGR1rs> {
758        SPICKSEL_W::new(self, 2)
759    }
760    ///Bit 5 - SCDEN
761    #[inline(always)]
762    pub fn scden(&mut self) -> SCDEN_W<CFGR1rs> {
763        SCDEN_W::new(self, 5)
764    }
765    ///Bit 6 - CKABEN
766    #[inline(always)]
767    pub fn ckaben(&mut self) -> CKABEN_W<CFGR1rs> {
768        CKABEN_W::new(self, 6)
769    }
770    ///Bit 7 - CHEN
771    #[inline(always)]
772    pub fn chen(&mut self) -> CHEN_W<CFGR1rs> {
773        CHEN_W::new(self, 7)
774    }
775    ///Bit 8 - CHINSEL
776    #[inline(always)]
777    pub fn chinsel(&mut self) -> CHINSEL_W<CFGR1rs> {
778        CHINSEL_W::new(self, 8)
779    }
780    ///Bits 12:13 - DATMPX
781    #[inline(always)]
782    pub fn datmpx(&mut self) -> DATMPX_W<CFGR1rs> {
783        DATMPX_W::new(self, 12)
784    }
785    ///Bits 14:15 - DATPACK
786    #[inline(always)]
787    pub fn datpack(&mut self) -> DATPACK_W<CFGR1rs> {
788        DATPACK_W::new(self, 14)
789    }
790    ///Bits 16:23 - CKOUTDIV
791    #[inline(always)]
792    pub fn ckoutdiv(&mut self) -> CKOUTDIV_W<CFGR1rs> {
793        CKOUTDIV_W::new(self, 16)
794    }
795    ///Bit 30 - CKOUTSRC
796    #[inline(always)]
797    pub fn ckoutsrc(&mut self) -> CKOUTSRC_W<CFGR1rs> {
798        CKOUTSRC_W::new(self, 30)
799    }
800    ///Bit 31 - DFSDMEN
801    #[inline(always)]
802    pub fn dfsdmen(&mut self) -> DFSDMEN_W<CFGR1rs> {
803        DFSDMEN_W::new(self, 31)
804    }
805}
806/**channel configuration y register
807
808You can [`read`](crate::Reg::read) this register and get [`cfgr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
809pub struct CFGR1rs;
810impl crate::RegisterSpec for CFGR1rs {
811    type Ux = u32;
812}
813///`read()` method returns [`cfgr1::R`](R) reader structure
814impl crate::Readable for CFGR1rs {}
815///`write(|w| ..)` method takes [`cfgr1::W`](W) writer structure
816impl crate::Writable for CFGR1rs {
817    type Safety = crate::Unsafe;
818}
819///`reset()` method sets CFGR1 to value 0
820impl crate::Resettable for CFGR1rs {}
stm32l4/stm32l4x5/dfsdm/ch/cfgr1.rs

stm32l4/stm32l4x5/dfsdm/ch/
cfgr1.rs
