stm32l4/stm32l4x5/adc1/
sqr4.rs

1///Register `SQR4` reader
2pub type R = crate::R<SQR4rs>;
3///Register `SQR4` writer
4pub type W = crate::W<SQR4rs>;
5///Field `SQ(15-16)` reader - %s conversion in regular sequence
6pub type SQ_R = crate::FieldReader;
7///Field `SQ(15-16)` writer - %s conversion in regular sequence
8pub type SQ_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9impl R {
10    ///(15-16) conversion in regular sequence
11    ///
12    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ15` field.</div>
13    #[inline(always)]
14    pub fn sq(&self, n: u8) -> SQ_R {
15        #[allow(clippy::no_effect)]
16        [(); 2][n as usize];
17        SQ_R::new(((self.bits >> (n * 6)) & 0x1f) as u8)
18    }
19    ///Iterator for array of:
20    ///(15-16) conversion in regular sequence
21    #[inline(always)]
22    pub fn sq_iter(&self) -> impl Iterator<Item = SQ_R> + '_ {
23        (0..2).map(move |n| SQ_R::new(((self.bits >> (n * 6)) & 0x1f) as u8))
24    }
25    ///Bits 0:4 - 15 conversion in regular sequence
26    #[inline(always)]
27    pub fn sq15(&self) -> SQ_R {
28        SQ_R::new((self.bits & 0x1f) as u8)
29    }
30    ///Bits 6:10 - 16 conversion in regular sequence
31    #[inline(always)]
32    pub fn sq16(&self) -> SQ_R {
33        SQ_R::new(((self.bits >> 6) & 0x1f) as u8)
34    }
35}
36impl core::fmt::Debug for R {
37    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
38        f.debug_struct("SQR4")
39            .field("sq15", &self.sq15())
40            .field("sq16", &self.sq16())
41            .finish()
42    }
43}
44impl W {
45    ///(15-16) conversion in regular sequence
46    ///
47    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ15` field.</div>
48    #[inline(always)]
49    pub fn sq(&mut self, n: u8) -> SQ_W<SQR4rs> {
50        #[allow(clippy::no_effect)]
51        [(); 2][n as usize];
52        SQ_W::new(self, n * 6)
53    }
54    ///Bits 0:4 - 15 conversion in regular sequence
55    #[inline(always)]
56    pub fn sq15(&mut self) -> SQ_W<SQR4rs> {
57        SQ_W::new(self, 0)
58    }
59    ///Bits 6:10 - 16 conversion in regular sequence
60    #[inline(always)]
61    pub fn sq16(&mut self) -> SQ_W<SQR4rs> {
62        SQ_W::new(self, 6)
63    }
64}
65/**regular sequence register 4
66
67You can [`read`](crate::Reg::read) this register and get [`sqr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
68
69See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#ADC1:SQR4)*/
70pub struct SQR4rs;
71impl crate::RegisterSpec for SQR4rs {
72    type Ux = u32;
73}
74///`read()` method returns [`sqr4::R`](R) reader structure
75impl crate::Readable for SQR4rs {}
76///`write(|w| ..)` method takes [`sqr4::W`](W) writer structure
77impl crate::Writable for SQR4rs {
78    type Safety = crate::Unsafe;
79}
80///`reset()` method sets SQR4 to value 0
81impl crate::Resettable for SQR4rs {}
stm32l4/stm32l4x5/adc1/sqr4.rs

stm32l4/stm32l4x5/adc1/
sqr4.rs
