stm32l4/stm32l4x5/adc1/
sqr1.rs

1///Register `SQR1` reader
2pub type R = crate::R<SQR1rs>;
3///Register `SQR1` writer
4pub type W = crate::W<SQR1rs>;
5///Field `L` reader - Regular channel sequence length
6pub type L_R = crate::FieldReader;
7///Field `L` writer - Regular channel sequence length
8pub type L_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
9///Field `SQ(1-4)` reader - %s conversion in regular sequence
10pub type SQ_R = crate::FieldReader;
11///Field `SQ(1-4)` writer - %s conversion in regular sequence
12pub type SQ_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13impl R {
14    ///Bits 0:3 - Regular channel sequence length
15    #[inline(always)]
16    pub fn l(&self) -> L_R {
17        L_R::new((self.bits & 0x0f) as u8)
18    }
19    ///(1-4) conversion in regular sequence
20    ///
21    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ1` field.</div>
22    #[inline(always)]
23    pub fn sq(&self, n: u8) -> SQ_R {
24        #[allow(clippy::no_effect)]
25        [(); 4][n as usize];
26        SQ_R::new(((self.bits >> (n * 6 + 6)) & 0x1f) as u8)
27    }
28    ///Iterator for array of:
29    ///(1-4) conversion in regular sequence
30    #[inline(always)]
31    pub fn sq_iter(&self) -> impl Iterator<Item = SQ_R> + '_ {
32        (0..4).map(move |n| SQ_R::new(((self.bits >> (n * 6 + 6)) & 0x1f) as u8))
33    }
34    ///Bits 6:10 - 1 conversion in regular sequence
35    #[inline(always)]
36    pub fn sq1(&self) -> SQ_R {
37        SQ_R::new(((self.bits >> 6) & 0x1f) as u8)
38    }
39    ///Bits 12:16 - 2 conversion in regular sequence
40    #[inline(always)]
41    pub fn sq2(&self) -> SQ_R {
42        SQ_R::new(((self.bits >> 12) & 0x1f) as u8)
43    }
44    ///Bits 18:22 - 3 conversion in regular sequence
45    #[inline(always)]
46    pub fn sq3(&self) -> SQ_R {
47        SQ_R::new(((self.bits >> 18) & 0x1f) as u8)
48    }
49    ///Bits 24:28 - 4 conversion in regular sequence
50    #[inline(always)]
51    pub fn sq4(&self) -> SQ_R {
52        SQ_R::new(((self.bits >> 24) & 0x1f) as u8)
53    }
54}
55impl core::fmt::Debug for R {
56    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
57        f.debug_struct("SQR1")
58            .field("sq1", &self.sq1())
59            .field("sq2", &self.sq2())
60            .field("sq3", &self.sq3())
61            .field("sq4", &self.sq4())
62            .field("l", &self.l())
63            .finish()
64    }
65}
66impl W {
67    ///Bits 0:3 - Regular channel sequence length
68    #[inline(always)]
69    pub fn l(&mut self) -> L_W<SQR1rs> {
70        L_W::new(self, 0)
71    }
72    ///(1-4) conversion in regular sequence
73    ///
74    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ1` field.</div>
75    #[inline(always)]
76    pub fn sq(&mut self, n: u8) -> SQ_W<SQR1rs> {
77        #[allow(clippy::no_effect)]
78        [(); 4][n as usize];
79        SQ_W::new(self, n * 6 + 6)
80    }
81    ///Bits 6:10 - 1 conversion in regular sequence
82    #[inline(always)]
83    pub fn sq1(&mut self) -> SQ_W<SQR1rs> {
84        SQ_W::new(self, 6)
85    }
86    ///Bits 12:16 - 2 conversion in regular sequence
87    #[inline(always)]
88    pub fn sq2(&mut self) -> SQ_W<SQR1rs> {
89        SQ_W::new(self, 12)
90    }
91    ///Bits 18:22 - 3 conversion in regular sequence
92    #[inline(always)]
93    pub fn sq3(&mut self) -> SQ_W<SQR1rs> {
94        SQ_W::new(self, 18)
95    }
96    ///Bits 24:28 - 4 conversion in regular sequence
97    #[inline(always)]
98    pub fn sq4(&mut self) -> SQ_W<SQR1rs> {
99        SQ_W::new(self, 24)
100    }
101}
102/**regular sequence register 1
103
104You can [`read`](crate::Reg::read) this register and get [`sqr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
105
106See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#ADC1:SQR1)*/
107pub struct SQR1rs;
108impl crate::RegisterSpec for SQR1rs {
109    type Ux = u32;
110}
111///`read()` method returns [`sqr1::R`](R) reader structure
112impl crate::Readable for SQR1rs {}
113///`write(|w| ..)` method takes [`sqr1::W`](W) writer structure
114impl crate::Writable for SQR1rs {
115    type Safety = crate::Unsafe;
116}
117///`reset()` method sets SQR1 to value 0
118impl crate::Resettable for SQR1rs {}
stm32l4/stm32l4x5/adc1/sqr1.rs

stm32l4/stm32l4x5/adc1/
sqr1.rs
