stm32l4/stm32l4x5/adc1/
awd3cr.rs

1///Register `AWD3CR` reader
2pub type R = crate::R<AWD3CRrs>;
3///Register `AWD3CR` writer
4pub type W = crate::W<AWD3CRrs>;
5/**AWD3CH
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum AWD3CH0 {
11    ///0: Input channel not monitored by AWDx
12    NotMonitored = 0,
13    ///1: Input channel monitored by AWDx
14    Monitored = 1,
15}
16impl From<AWD3CH0> for bool {
17    #[inline(always)]
18    fn from(variant: AWD3CH0) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `AWD3CH(0-17)` reader - AWD3CH
23pub type AWD3CH_R = crate::BitReader<AWD3CH0>;
24impl AWD3CH_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> AWD3CH0 {
28        match self.bits {
29            false => AWD3CH0::NotMonitored,
30            true => AWD3CH0::Monitored,
31        }
32    }
33    ///Input channel not monitored by AWDx
34    #[inline(always)]
35    pub fn is_not_monitored(&self) -> bool {
36        *self == AWD3CH0::NotMonitored
37    }
38    ///Input channel monitored by AWDx
39    #[inline(always)]
40    pub fn is_monitored(&self) -> bool {
41        *self == AWD3CH0::Monitored
42    }
43}
44///Field `AWD3CH(0-17)` writer - AWD3CH
45pub type AWD3CH_W<'a, REG> = crate::BitWriter<'a, REG, AWD3CH0>;
46impl<'a, REG> AWD3CH_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Input channel not monitored by AWDx
51    #[inline(always)]
52    pub fn not_monitored(self) -> &'a mut crate::W<REG> {
53        self.variant(AWD3CH0::NotMonitored)
54    }
55    ///Input channel monitored by AWDx
56    #[inline(always)]
57    pub fn monitored(self) -> &'a mut crate::W<REG> {
58        self.variant(AWD3CH0::Monitored)
59    }
60}
61impl R {
62    ///AWD3CH
63    ///
64    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD3CH0` field.</div>
65    #[inline(always)]
66    pub fn awd3ch(&self, n: u8) -> AWD3CH_R {
67        #[allow(clippy::no_effect)]
68        [(); 18][n as usize];
69        AWD3CH_R::new(((self.bits >> (n + 1)) & 1) != 0)
70    }
71    ///Iterator for array of:
72    ///AWD3CH
73    #[inline(always)]
74    pub fn awd3ch_iter(&self) -> impl Iterator<Item = AWD3CH_R> + '_ {
75        (0..18).map(move |n| AWD3CH_R::new(((self.bits >> (n + 1)) & 1) != 0))
76    }
77    ///Bit 1 - AWD3CH
78    #[inline(always)]
79    pub fn awd3ch0(&self) -> AWD3CH_R {
80        AWD3CH_R::new(((self.bits >> 1) & 1) != 0)
81    }
82    ///Bit 2 - AWD3CH
83    #[inline(always)]
84    pub fn awd3ch1(&self) -> AWD3CH_R {
85        AWD3CH_R::new(((self.bits >> 2) & 1) != 0)
86    }
87    ///Bit 3 - AWD3CH
88    #[inline(always)]
89    pub fn awd3ch2(&self) -> AWD3CH_R {
90        AWD3CH_R::new(((self.bits >> 3) & 1) != 0)
91    }
92    ///Bit 4 - AWD3CH
93    #[inline(always)]
94    pub fn awd3ch3(&self) -> AWD3CH_R {
95        AWD3CH_R::new(((self.bits >> 4) & 1) != 0)
96    }
97    ///Bit 5 - AWD3CH
98    #[inline(always)]
99    pub fn awd3ch4(&self) -> AWD3CH_R {
100        AWD3CH_R::new(((self.bits >> 5) & 1) != 0)
101    }
102    ///Bit 6 - AWD3CH
103    #[inline(always)]
104    pub fn awd3ch5(&self) -> AWD3CH_R {
105        AWD3CH_R::new(((self.bits >> 6) & 1) != 0)
106    }
107    ///Bit 7 - AWD3CH
108    #[inline(always)]
109    pub fn awd3ch6(&self) -> AWD3CH_R {
110        AWD3CH_R::new(((self.bits >> 7) & 1) != 0)
111    }
112    ///Bit 8 - AWD3CH
113    #[inline(always)]
114    pub fn awd3ch7(&self) -> AWD3CH_R {
115        AWD3CH_R::new(((self.bits >> 8) & 1) != 0)
116    }
117    ///Bit 9 - AWD3CH
118    #[inline(always)]
119    pub fn awd3ch8(&self) -> AWD3CH_R {
120        AWD3CH_R::new(((self.bits >> 9) & 1) != 0)
121    }
122    ///Bit 10 - AWD3CH
123    #[inline(always)]
124    pub fn awd3ch9(&self) -> AWD3CH_R {
125        AWD3CH_R::new(((self.bits >> 10) & 1) != 0)
126    }
127    ///Bit 11 - AWD3CH
128    #[inline(always)]
129    pub fn awd3ch10(&self) -> AWD3CH_R {
130        AWD3CH_R::new(((self.bits >> 11) & 1) != 0)
131    }
132    ///Bit 12 - AWD3CH
133    #[inline(always)]
134    pub fn awd3ch11(&self) -> AWD3CH_R {
135        AWD3CH_R::new(((self.bits >> 12) & 1) != 0)
136    }
137    ///Bit 13 - AWD3CH
138    #[inline(always)]
139    pub fn awd3ch12(&self) -> AWD3CH_R {
140        AWD3CH_R::new(((self.bits >> 13) & 1) != 0)
141    }
142    ///Bit 14 - AWD3CH
143    #[inline(always)]
144    pub fn awd3ch13(&self) -> AWD3CH_R {
145        AWD3CH_R::new(((self.bits >> 14) & 1) != 0)
146    }
147    ///Bit 15 - AWD3CH
148    #[inline(always)]
149    pub fn awd3ch14(&self) -> AWD3CH_R {
150        AWD3CH_R::new(((self.bits >> 15) & 1) != 0)
151    }
152    ///Bit 16 - AWD3CH
153    #[inline(always)]
154    pub fn awd3ch15(&self) -> AWD3CH_R {
155        AWD3CH_R::new(((self.bits >> 16) & 1) != 0)
156    }
157    ///Bit 17 - AWD3CH
158    #[inline(always)]
159    pub fn awd3ch16(&self) -> AWD3CH_R {
160        AWD3CH_R::new(((self.bits >> 17) & 1) != 0)
161    }
162    ///Bit 18 - AWD3CH
163    #[inline(always)]
164    pub fn awd3ch17(&self) -> AWD3CH_R {
165        AWD3CH_R::new(((self.bits >> 18) & 1) != 0)
166    }
167}
168impl core::fmt::Debug for R {
169    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
170        f.debug_struct("AWD3CR")
171            .field("awd3ch0", &self.awd3ch0())
172            .field("awd3ch1", &self.awd3ch1())
173            .field("awd3ch2", &self.awd3ch2())
174            .field("awd3ch3", &self.awd3ch3())
175            .field("awd3ch4", &self.awd3ch4())
176            .field("awd3ch5", &self.awd3ch5())
177            .field("awd3ch6", &self.awd3ch6())
178            .field("awd3ch7", &self.awd3ch7())
179            .field("awd3ch8", &self.awd3ch8())
180            .field("awd3ch9", &self.awd3ch9())
181            .field("awd3ch10", &self.awd3ch10())
182            .field("awd3ch11", &self.awd3ch11())
183            .field("awd3ch12", &self.awd3ch12())
184            .field("awd3ch13", &self.awd3ch13())
185            .field("awd3ch14", &self.awd3ch14())
186            .field("awd3ch15", &self.awd3ch15())
187            .field("awd3ch16", &self.awd3ch16())
188            .field("awd3ch17", &self.awd3ch17())
189            .finish()
190    }
191}
192impl W {
193    ///AWD3CH
194    ///
195    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD3CH0` field.</div>
196    #[inline(always)]
197    pub fn awd3ch(&mut self, n: u8) -> AWD3CH_W<AWD3CRrs> {
198        #[allow(clippy::no_effect)]
199        [(); 18][n as usize];
200        AWD3CH_W::new(self, n + 1)
201    }
202    ///Bit 1 - AWD3CH
203    #[inline(always)]
204    pub fn awd3ch0(&mut self) -> AWD3CH_W<AWD3CRrs> {
205        AWD3CH_W::new(self, 1)
206    }
207    ///Bit 2 - AWD3CH
208    #[inline(always)]
209    pub fn awd3ch1(&mut self) -> AWD3CH_W<AWD3CRrs> {
210        AWD3CH_W::new(self, 2)
211    }
212    ///Bit 3 - AWD3CH
213    #[inline(always)]
214    pub fn awd3ch2(&mut self) -> AWD3CH_W<AWD3CRrs> {
215        AWD3CH_W::new(self, 3)
216    }
217    ///Bit 4 - AWD3CH
218    #[inline(always)]
219    pub fn awd3ch3(&mut self) -> AWD3CH_W<AWD3CRrs> {
220        AWD3CH_W::new(self, 4)
221    }
222    ///Bit 5 - AWD3CH
223    #[inline(always)]
224    pub fn awd3ch4(&mut self) -> AWD3CH_W<AWD3CRrs> {
225        AWD3CH_W::new(self, 5)
226    }
227    ///Bit 6 - AWD3CH
228    #[inline(always)]
229    pub fn awd3ch5(&mut self) -> AWD3CH_W<AWD3CRrs> {
230        AWD3CH_W::new(self, 6)
231    }
232    ///Bit 7 - AWD3CH
233    #[inline(always)]
234    pub fn awd3ch6(&mut self) -> AWD3CH_W<AWD3CRrs> {
235        AWD3CH_W::new(self, 7)
236    }
237    ///Bit 8 - AWD3CH
238    #[inline(always)]
239    pub fn awd3ch7(&mut self) -> AWD3CH_W<AWD3CRrs> {
240        AWD3CH_W::new(self, 8)
241    }
242    ///Bit 9 - AWD3CH
243    #[inline(always)]
244    pub fn awd3ch8(&mut self) -> AWD3CH_W<AWD3CRrs> {
245        AWD3CH_W::new(self, 9)
246    }
247    ///Bit 10 - AWD3CH
248    #[inline(always)]
249    pub fn awd3ch9(&mut self) -> AWD3CH_W<AWD3CRrs> {
250        AWD3CH_W::new(self, 10)
251    }
252    ///Bit 11 - AWD3CH
253    #[inline(always)]
254    pub fn awd3ch10(&mut self) -> AWD3CH_W<AWD3CRrs> {
255        AWD3CH_W::new(self, 11)
256    }
257    ///Bit 12 - AWD3CH
258    #[inline(always)]
259    pub fn awd3ch11(&mut self) -> AWD3CH_W<AWD3CRrs> {
260        AWD3CH_W::new(self, 12)
261    }
262    ///Bit 13 - AWD3CH
263    #[inline(always)]
264    pub fn awd3ch12(&mut self) -> AWD3CH_W<AWD3CRrs> {
265        AWD3CH_W::new(self, 13)
266    }
267    ///Bit 14 - AWD3CH
268    #[inline(always)]
269    pub fn awd3ch13(&mut self) -> AWD3CH_W<AWD3CRrs> {
270        AWD3CH_W::new(self, 14)
271    }
272    ///Bit 15 - AWD3CH
273    #[inline(always)]
274    pub fn awd3ch14(&mut self) -> AWD3CH_W<AWD3CRrs> {
275        AWD3CH_W::new(self, 15)
276    }
277    ///Bit 16 - AWD3CH
278    #[inline(always)]
279    pub fn awd3ch15(&mut self) -> AWD3CH_W<AWD3CRrs> {
280        AWD3CH_W::new(self, 16)
281    }
282    ///Bit 17 - AWD3CH
283    #[inline(always)]
284    pub fn awd3ch16(&mut self) -> AWD3CH_W<AWD3CRrs> {
285        AWD3CH_W::new(self, 17)
286    }
287    ///Bit 18 - AWD3CH
288    #[inline(always)]
289    pub fn awd3ch17(&mut self) -> AWD3CH_W<AWD3CRrs> {
290        AWD3CH_W::new(self, 18)
291    }
292}
293/**Analog Watchdog 3 Configuration Register
294
295You can [`read`](crate::Reg::read) this register and get [`awd3cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd3cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
296
297See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x5.html#ADC1:AWD3CR)*/
298pub struct AWD3CRrs;
299impl crate::RegisterSpec for AWD3CRrs {
300    type Ux = u32;
301}
302///`read()` method returns [`awd3cr::R`](R) reader structure
303impl crate::Readable for AWD3CRrs {}
304///`write(|w| ..)` method takes [`awd3cr::W`](W) writer structure
305impl crate::Writable for AWD3CRrs {
306    type Safety = crate::Unsafe;
307}
308///`reset()` method sets AWD3CR to value 0
309impl crate::Resettable for AWD3CRrs {}
stm32l4/stm32l4x5/adc1/awd3cr.rs

stm32l4/stm32l4x5/adc1/
awd3cr.rs
