stm32l4/stm32l4x1/tim8/
or1.rs

1///Register `OR1` reader
2pub type R = crate::R<OR1rs>;
3///Register `OR1` writer
4pub type W = crate::W<OR1rs>;
5///Field `ETR_ADC2_RMP` reader - External trigger remap on ADC2 analog watchdog
6pub type ETR_ADC2_RMP_R = crate::FieldReader;
7///Field `ETR_ADC2_RMP` writer - External trigger remap on ADC2 analog watchdog
8pub type ETR_ADC2_RMP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9///Field `ETR_ADC3_RMP` reader - External trigger remap on ADC3 analog watchdog
10pub type ETR_ADC3_RMP_R = crate::FieldReader;
11///Field `ETR_ADC3_RMP` writer - External trigger remap on ADC3 analog watchdog
12pub type ETR_ADC3_RMP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13///Field `TI1_RMP` reader - Input Capture 1 remap
14pub type TI1_RMP_R = crate::BitReader;
15///Field `TI1_RMP` writer - Input Capture 1 remap
16pub type TI1_RMP_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    ///Bits 0:1 - External trigger remap on ADC2 analog watchdog
19    #[inline(always)]
20    pub fn etr_adc2_rmp(&self) -> ETR_ADC2_RMP_R {
21        ETR_ADC2_RMP_R::new((self.bits & 3) as u8)
22    }
23    ///Bits 2:3 - External trigger remap on ADC3 analog watchdog
24    #[inline(always)]
25    pub fn etr_adc3_rmp(&self) -> ETR_ADC3_RMP_R {
26        ETR_ADC3_RMP_R::new(((self.bits >> 2) & 3) as u8)
27    }
28    ///Bit 4 - Input Capture 1 remap
29    #[inline(always)]
30    pub fn ti1_rmp(&self) -> TI1_RMP_R {
31        TI1_RMP_R::new(((self.bits >> 4) & 1) != 0)
32    }
33}
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("OR1")
37            .field("etr_adc2_rmp", &self.etr_adc2_rmp())
38            .field("etr_adc3_rmp", &self.etr_adc3_rmp())
39            .field("ti1_rmp", &self.ti1_rmp())
40            .finish()
41    }
42}
43impl W {
44    ///Bits 0:1 - External trigger remap on ADC2 analog watchdog
45    #[inline(always)]
46    pub fn etr_adc2_rmp(&mut self) -> ETR_ADC2_RMP_W<OR1rs> {
47        ETR_ADC2_RMP_W::new(self, 0)
48    }
49    ///Bits 2:3 - External trigger remap on ADC3 analog watchdog
50    #[inline(always)]
51    pub fn etr_adc3_rmp(&mut self) -> ETR_ADC3_RMP_W<OR1rs> {
52        ETR_ADC3_RMP_W::new(self, 2)
53    }
54    ///Bit 4 - Input Capture 1 remap
55    #[inline(always)]
56    pub fn ti1_rmp(&mut self) -> TI1_RMP_W<OR1rs> {
57        TI1_RMP_W::new(self, 4)
58    }
59}
60/**TIM8 option register 1
61
62You can [`read`](crate::Reg::read) this register and get [`or1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`or1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
63
64See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#TIM8:OR1)*/
65pub struct OR1rs;
66impl crate::RegisterSpec for OR1rs {
67    type Ux = u32;
68}
69///`read()` method returns [`or1::R`](R) reader structure
70impl crate::Readable for OR1rs {}
71///`write(|w| ..)` method takes [`or1::W`](W) writer structure
72impl crate::Writable for OR1rs {
73    type Safety = crate::Unsafe;
74}
75///`reset()` method sets OR1 to value 0
76impl crate::Resettable for OR1rs {}
stm32l4/stm32l4x1/tim8/or1.rs

stm32l4/stm32l4x1/tim8/
or1.rs
