stm32l4/stm32l4x1/tim15/
egr.rs

1///Register `EGR` reader
2pub type R = crate::R<EGRrs>;
3///Register `EGR` writer
4pub type W = crate::W<EGRrs>;
5/**Update generation
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum UG {
11    ///1: Re-initializes the timer counter and generates an update of the registers.
12    Update = 1,
13}
14impl From<UG> for bool {
15    #[inline(always)]
16    fn from(variant: UG) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `UG` writer - Update generation
21pub type UG_W<'a, REG> = crate::BitWriter<'a, REG, UG>;
22impl<'a, REG> UG_W<'a, REG>
23where
24    REG: crate::Writable + crate::RegisterSpec,
25{
26    ///Re-initializes the timer counter and generates an update of the registers.
27    #[inline(always)]
28    pub fn update(self) -> &'a mut crate::W<REG> {
29        self.variant(UG::Update)
30    }
31}
32/**Capture/compare %s generation
33
34Value on reset: 0*/
35#[cfg_attr(feature = "defmt", derive(defmt::Format))]
36#[derive(Clone, Copy, Debug, PartialEq, Eq)]
37pub enum CC1GW {
38    ///1: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
39    Trigger = 1,
40}
41impl From<CC1GW> for bool {
42    #[inline(always)]
43    fn from(variant: CC1GW) -> Self {
44        variant as u8 != 0
45    }
46}
47///Field `CCG(1-2)` writer - Capture/compare %s generation
48pub type CCG_W<'a, REG> = crate::BitWriter<'a, REG, CC1GW>;
49impl<'a, REG> CCG_W<'a, REG>
50where
51    REG: crate::Writable + crate::RegisterSpec,
52{
53    ///If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
54    #[inline(always)]
55    pub fn trigger(self) -> &'a mut crate::W<REG> {
56        self.variant(CC1GW::Trigger)
57    }
58}
59/**Capture/Compare control update generation
60
61Value on reset: 0*/
62#[cfg_attr(feature = "defmt", derive(defmt::Format))]
63#[derive(Clone, Copy, Debug, PartialEq, Eq)]
64pub enum COMGW {
65    ///1: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
66    Trigger = 1,
67}
68impl From<COMGW> for bool {
69    #[inline(always)]
70    fn from(variant: COMGW) -> Self {
71        variant as u8 != 0
72    }
73}
74///Field `COMG` reader - Capture/Compare control update generation
75pub type COMG_R = crate::BitReader<COMGW>;
76impl COMG_R {
77    ///Get enumerated values variant
78    #[inline(always)]
79    pub const fn variant(&self) -> Option<COMGW> {
80        match self.bits {
81            true => Some(COMGW::Trigger),
82            _ => None,
83        }
84    }
85    ///When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
86    #[inline(always)]
87    pub fn is_trigger(&self) -> bool {
88        *self == COMGW::Trigger
89    }
90}
91///Field `COMG` writer - Capture/Compare control update generation
92pub type COMG_W<'a, REG> = crate::BitWriter<'a, REG, COMGW>;
93impl<'a, REG> COMG_W<'a, REG>
94where
95    REG: crate::Writable + crate::RegisterSpec,
96{
97    ///When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
98    #[inline(always)]
99    pub fn trigger(self) -> &'a mut crate::W<REG> {
100        self.variant(COMGW::Trigger)
101    }
102}
103/**Trigger generation
104
105Value on reset: 0*/
106#[cfg_attr(feature = "defmt", derive(defmt::Format))]
107#[derive(Clone, Copy, Debug, PartialEq, Eq)]
108pub enum TGW {
109    ///1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
110    Trigger = 1,
111}
112impl From<TGW> for bool {
113    #[inline(always)]
114    fn from(variant: TGW) -> Self {
115        variant as u8 != 0
116    }
117}
118///Field `TG` writer - Trigger generation
119pub type TG_W<'a, REG> = crate::BitWriter<'a, REG, TGW>;
120impl<'a, REG> TG_W<'a, REG>
121where
122    REG: crate::Writable + crate::RegisterSpec,
123{
124    ///The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
125    #[inline(always)]
126    pub fn trigger(self) -> &'a mut crate::W<REG> {
127        self.variant(TGW::Trigger)
128    }
129}
130/**Break generation
131
132Value on reset: 0*/
133#[cfg_attr(feature = "defmt", derive(defmt::Format))]
134#[derive(Clone, Copy, Debug, PartialEq, Eq)]
135pub enum BGW {
136    ///1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
137    Trigger = 1,
138}
139impl From<BGW> for bool {
140    #[inline(always)]
141    fn from(variant: BGW) -> Self {
142        variant as u8 != 0
143    }
144}
145///Field `BG` writer - Break generation
146pub type BG_W<'a, REG> = crate::BitWriter<'a, REG, BGW>;
147impl<'a, REG> BG_W<'a, REG>
148where
149    REG: crate::Writable + crate::RegisterSpec,
150{
151    ///A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
152    #[inline(always)]
153    pub fn trigger(self) -> &'a mut crate::W<REG> {
154        self.variant(BGW::Trigger)
155    }
156}
157impl R {
158    ///Bit 5 - Capture/Compare control update generation
159    #[inline(always)]
160    pub fn comg(&self) -> COMG_R {
161        COMG_R::new(((self.bits >> 5) & 1) != 0)
162    }
163}
164impl core::fmt::Debug for R {
165    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
166        f.debug_struct("EGR").field("comg", &self.comg()).finish()
167    }
168}
169impl W {
170    ///Bit 0 - Update generation
171    #[inline(always)]
172    pub fn ug(&mut self) -> UG_W<EGRrs> {
173        UG_W::new(self, 0)
174    }
175    ///Capture/compare (1-2) generation
176    ///
177    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1G` field.</div>
178    #[inline(always)]
179    pub fn ccg(&mut self, n: u8) -> CCG_W<EGRrs> {
180        #[allow(clippy::no_effect)]
181        [(); 2][n as usize];
182        CCG_W::new(self, n + 1)
183    }
184    ///Bit 1 - Capture/compare 1 generation
185    #[inline(always)]
186    pub fn cc1g(&mut self) -> CCG_W<EGRrs> {
187        CCG_W::new(self, 1)
188    }
189    ///Bit 2 - Capture/compare 2 generation
190    #[inline(always)]
191    pub fn cc2g(&mut self) -> CCG_W<EGRrs> {
192        CCG_W::new(self, 2)
193    }
194    ///Bit 5 - Capture/Compare control update generation
195    #[inline(always)]
196    pub fn comg(&mut self) -> COMG_W<EGRrs> {
197        COMG_W::new(self, 5)
198    }
199    ///Bit 6 - Trigger generation
200    #[inline(always)]
201    pub fn tg(&mut self) -> TG_W<EGRrs> {
202        TG_W::new(self, 6)
203    }
204    ///Bit 7 - Break generation
205    #[inline(always)]
206    pub fn bg(&mut self) -> BG_W<EGRrs> {
207        BG_W::new(self, 7)
208    }
209}
210/**event generation register
211
212You can [`read`](crate::Reg::read) this register and get [`egr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
213
214See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#TIM15:EGR)*/
215pub struct EGRrs;
216impl crate::RegisterSpec for EGRrs {
217    type Ux = u32;
218}
219///`read()` method returns [`egr::R`](R) reader structure
220impl crate::Readable for EGRrs {}
221///`write(|w| ..)` method takes [`egr::W`](W) writer structure
222impl crate::Writable for EGRrs {
223    type Safety = crate::Unsafe;
224}
225///`reset()` method sets EGR to value 0
226impl crate::Resettable for EGRrs {}
stm32l4/stm32l4x1/tim15/egr.rs

stm32l4/stm32l4x1/tim15/
egr.rs
