stm32l4/stm32l4x1/tim1/
bdtr.rs

1///Register `BDTR` reader
2pub type R = crate::R<BDTRrs>;
3///Register `BDTR` writer
4pub type W = crate::W<BDTRrs>;
5///Field `DTG` reader - Dead-time generator setup
6pub type DTG_R = crate::FieldReader;
7///Field `DTG` writer - Dead-time generator setup
8pub type DTG_W<'a, REG> = crate::FieldWriter<'a, REG, 8, u8, crate::Safe>;
9/**Lock configuration
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14#[repr(u8)]
15pub enum LOCK {
16    ///0: No bit is write protected
17    Off = 0,
18    ///1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
19    Level1 = 1,
20    ///2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
21    Level2 = 2,
22    ///3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
23    Level3 = 3,
24}
25impl From<LOCK> for u8 {
26    #[inline(always)]
27    fn from(variant: LOCK) -> Self {
28        variant as _
29    }
30}
31impl crate::FieldSpec for LOCK {
32    type Ux = u8;
33}
34impl crate::IsEnum for LOCK {}
35///Field `LOCK` reader - Lock configuration
36pub type LOCK_R = crate::FieldReader<LOCK>;
37impl LOCK_R {
38    ///Get enumerated values variant
39    #[inline(always)]
40    pub const fn variant(&self) -> LOCK {
41        match self.bits {
42            0 => LOCK::Off,
43            1 => LOCK::Level1,
44            2 => LOCK::Level2,
45            3 => LOCK::Level3,
46            _ => unreachable!(),
47        }
48    }
49    ///No bit is write protected
50    #[inline(always)]
51    pub fn is_off(&self) -> bool {
52        *self == LOCK::Off
53    }
54    ///Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
55    #[inline(always)]
56    pub fn is_level1(&self) -> bool {
57        *self == LOCK::Level1
58    }
59    ///LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
60    #[inline(always)]
61    pub fn is_level2(&self) -> bool {
62        *self == LOCK::Level2
63    }
64    ///LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
65    #[inline(always)]
66    pub fn is_level3(&self) -> bool {
67        *self == LOCK::Level3
68    }
69}
70///Field `LOCK` writer - Lock configuration
71pub type LOCK_W<'a, REG> = crate::FieldWriter<'a, REG, 2, LOCK, crate::Safe>;
72impl<'a, REG> LOCK_W<'a, REG>
73where
74    REG: crate::Writable + crate::RegisterSpec,
75    REG::Ux: From<u8>,
76{
77    ///No bit is write protected
78    #[inline(always)]
79    pub fn off(self) -> &'a mut crate::W<REG> {
80        self.variant(LOCK::Off)
81    }
82    ///Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
83    #[inline(always)]
84    pub fn level1(self) -> &'a mut crate::W<REG> {
85        self.variant(LOCK::Level1)
86    }
87    ///LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
88    #[inline(always)]
89    pub fn level2(self) -> &'a mut crate::W<REG> {
90        self.variant(LOCK::Level2)
91    }
92    ///LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
93    #[inline(always)]
94    pub fn level3(self) -> &'a mut crate::W<REG> {
95        self.variant(LOCK::Level3)
96    }
97}
98/**Off-state selection for Idle mode
99
100Value on reset: 0*/
101#[cfg_attr(feature = "defmt", derive(defmt::Format))]
102#[derive(Clone, Copy, Debug, PartialEq, Eq)]
103pub enum OSSI {
104    ///0: When inactive, OC/OCN outputs are disabled
105    HiZ = 0,
106    ///1: When inactive, OC/OCN outputs are forced to idle level
107    IdleLevel = 1,
108}
109impl From<OSSI> for bool {
110    #[inline(always)]
111    fn from(variant: OSSI) -> Self {
112        variant as u8 != 0
113    }
114}
115///Field `OSSI` reader - Off-state selection for Idle mode
116pub type OSSI_R = crate::BitReader<OSSI>;
117impl OSSI_R {
118    ///Get enumerated values variant
119    #[inline(always)]
120    pub const fn variant(&self) -> OSSI {
121        match self.bits {
122            false => OSSI::HiZ,
123            true => OSSI::IdleLevel,
124        }
125    }
126    ///When inactive, OC/OCN outputs are disabled
127    #[inline(always)]
128    pub fn is_hi_z(&self) -> bool {
129        *self == OSSI::HiZ
130    }
131    ///When inactive, OC/OCN outputs are forced to idle level
132    #[inline(always)]
133    pub fn is_idle_level(&self) -> bool {
134        *self == OSSI::IdleLevel
135    }
136}
137///Field `OSSI` writer - Off-state selection for Idle mode
138pub type OSSI_W<'a, REG> = crate::BitWriter<'a, REG, OSSI>;
139impl<'a, REG> OSSI_W<'a, REG>
140where
141    REG: crate::Writable + crate::RegisterSpec,
142{
143    ///When inactive, OC/OCN outputs are disabled
144    #[inline(always)]
145    pub fn hi_z(self) -> &'a mut crate::W<REG> {
146        self.variant(OSSI::HiZ)
147    }
148    ///When inactive, OC/OCN outputs are forced to idle level
149    #[inline(always)]
150    pub fn idle_level(self) -> &'a mut crate::W<REG> {
151        self.variant(OSSI::IdleLevel)
152    }
153}
154/**Off-state selection for Run mode
155
156Value on reset: 0*/
157#[cfg_attr(feature = "defmt", derive(defmt::Format))]
158#[derive(Clone, Copy, Debug, PartialEq, Eq)]
159pub enum OSSR {
160    ///0: When inactive, OC/OCN outputs are disabled
161    HiZ = 0,
162    ///1: When inactive, OC/OCN outputs are enabled with their inactive level
163    IdleLevel = 1,
164}
165impl From<OSSR> for bool {
166    #[inline(always)]
167    fn from(variant: OSSR) -> Self {
168        variant as u8 != 0
169    }
170}
171///Field `OSSR` reader - Off-state selection for Run mode
172pub type OSSR_R = crate::BitReader<OSSR>;
173impl OSSR_R {
174    ///Get enumerated values variant
175    #[inline(always)]
176    pub const fn variant(&self) -> OSSR {
177        match self.bits {
178            false => OSSR::HiZ,
179            true => OSSR::IdleLevel,
180        }
181    }
182    ///When inactive, OC/OCN outputs are disabled
183    #[inline(always)]
184    pub fn is_hi_z(&self) -> bool {
185        *self == OSSR::HiZ
186    }
187    ///When inactive, OC/OCN outputs are enabled with their inactive level
188    #[inline(always)]
189    pub fn is_idle_level(&self) -> bool {
190        *self == OSSR::IdleLevel
191    }
192}
193///Field `OSSR` writer - Off-state selection for Run mode
194pub type OSSR_W<'a, REG> = crate::BitWriter<'a, REG, OSSR>;
195impl<'a, REG> OSSR_W<'a, REG>
196where
197    REG: crate::Writable + crate::RegisterSpec,
198{
199    ///When inactive, OC/OCN outputs are disabled
200    #[inline(always)]
201    pub fn hi_z(self) -> &'a mut crate::W<REG> {
202        self.variant(OSSR::HiZ)
203    }
204    ///When inactive, OC/OCN outputs are enabled with their inactive level
205    #[inline(always)]
206    pub fn idle_level(self) -> &'a mut crate::W<REG> {
207        self.variant(OSSR::IdleLevel)
208    }
209}
210/**Break enable
211
212Value on reset: 0*/
213#[cfg_attr(feature = "defmt", derive(defmt::Format))]
214#[derive(Clone, Copy, Debug, PartialEq, Eq)]
215pub enum BKE {
216    ///0: Break function x disabled
217    Disabled = 0,
218    ///1: Break function x enabled
219    Enabled = 1,
220}
221impl From<BKE> for bool {
222    #[inline(always)]
223    fn from(variant: BKE) -> Self {
224        variant as u8 != 0
225    }
226}
227///Field `BKE` reader - Break enable
228pub type BKE_R = crate::BitReader<BKE>;
229impl BKE_R {
230    ///Get enumerated values variant
231    #[inline(always)]
232    pub const fn variant(&self) -> BKE {
233        match self.bits {
234            false => BKE::Disabled,
235            true => BKE::Enabled,
236        }
237    }
238    ///Break function x disabled
239    #[inline(always)]
240    pub fn is_disabled(&self) -> bool {
241        *self == BKE::Disabled
242    }
243    ///Break function x enabled
244    #[inline(always)]
245    pub fn is_enabled(&self) -> bool {
246        *self == BKE::Enabled
247    }
248}
249///Field `BKE` writer - Break enable
250pub type BKE_W<'a, REG> = crate::BitWriter<'a, REG, BKE>;
251impl<'a, REG> BKE_W<'a, REG>
252where
253    REG: crate::Writable + crate::RegisterSpec,
254{
255    ///Break function x disabled
256    #[inline(always)]
257    pub fn disabled(self) -> &'a mut crate::W<REG> {
258        self.variant(BKE::Disabled)
259    }
260    ///Break function x enabled
261    #[inline(always)]
262    pub fn enabled(self) -> &'a mut crate::W<REG> {
263        self.variant(BKE::Enabled)
264    }
265}
266/**Break polarity
267
268Value on reset: 0*/
269#[cfg_attr(feature = "defmt", derive(defmt::Format))]
270#[derive(Clone, Copy, Debug, PartialEq, Eq)]
271pub enum BKP {
272    ///0: Break input BRKx is active low
273    ActiveLow = 0,
274    ///1: Break input BRKx is active high
275    ActiveHigh = 1,
276}
277impl From<BKP> for bool {
278    #[inline(always)]
279    fn from(variant: BKP) -> Self {
280        variant as u8 != 0
281    }
282}
283///Field `BKP` reader - Break polarity
284pub type BKP_R = crate::BitReader<BKP>;
285impl BKP_R {
286    ///Get enumerated values variant
287    #[inline(always)]
288    pub const fn variant(&self) -> BKP {
289        match self.bits {
290            false => BKP::ActiveLow,
291            true => BKP::ActiveHigh,
292        }
293    }
294    ///Break input BRKx is active low
295    #[inline(always)]
296    pub fn is_active_low(&self) -> bool {
297        *self == BKP::ActiveLow
298    }
299    ///Break input BRKx is active high
300    #[inline(always)]
301    pub fn is_active_high(&self) -> bool {
302        *self == BKP::ActiveHigh
303    }
304}
305///Field `BKP` writer - Break polarity
306pub type BKP_W<'a, REG> = crate::BitWriter<'a, REG, BKP>;
307impl<'a, REG> BKP_W<'a, REG>
308where
309    REG: crate::Writable + crate::RegisterSpec,
310{
311    ///Break input BRKx is active low
312    #[inline(always)]
313    pub fn active_low(self) -> &'a mut crate::W<REG> {
314        self.variant(BKP::ActiveLow)
315    }
316    ///Break input BRKx is active high
317    #[inline(always)]
318    pub fn active_high(self) -> &'a mut crate::W<REG> {
319        self.variant(BKP::ActiveHigh)
320    }
321}
322/**Automatic output enable
323
324Value on reset: 0*/
325#[cfg_attr(feature = "defmt", derive(defmt::Format))]
326#[derive(Clone, Copy, Debug, PartialEq, Eq)]
327pub enum AOE {
328    ///0: MOE can be set only by software
329    Manual = 0,
330    ///1: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
331    Automatic = 1,
332}
333impl From<AOE> for bool {
334    #[inline(always)]
335    fn from(variant: AOE) -> Self {
336        variant as u8 != 0
337    }
338}
339///Field `AOE` reader - Automatic output enable
340pub type AOE_R = crate::BitReader<AOE>;
341impl AOE_R {
342    ///Get enumerated values variant
343    #[inline(always)]
344    pub const fn variant(&self) -> AOE {
345        match self.bits {
346            false => AOE::Manual,
347            true => AOE::Automatic,
348        }
349    }
350    ///MOE can be set only by software
351    #[inline(always)]
352    pub fn is_manual(&self) -> bool {
353        *self == AOE::Manual
354    }
355    ///MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
356    #[inline(always)]
357    pub fn is_automatic(&self) -> bool {
358        *self == AOE::Automatic
359    }
360}
361///Field `AOE` writer - Automatic output enable
362pub type AOE_W<'a, REG> = crate::BitWriter<'a, REG, AOE>;
363impl<'a, REG> AOE_W<'a, REG>
364where
365    REG: crate::Writable + crate::RegisterSpec,
366{
367    ///MOE can be set only by software
368    #[inline(always)]
369    pub fn manual(self) -> &'a mut crate::W<REG> {
370        self.variant(AOE::Manual)
371    }
372    ///MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
373    #[inline(always)]
374    pub fn automatic(self) -> &'a mut crate::W<REG> {
375        self.variant(AOE::Automatic)
376    }
377}
378/**Main output enable
379
380Value on reset: 0*/
381#[cfg_attr(feature = "defmt", derive(defmt::Format))]
382#[derive(Clone, Copy, Debug, PartialEq, Eq)]
383pub enum MOE {
384    ///0: OC/OCN are disabled or forced idle depending on OSSI
385    DisabledIdle = 0,
386    ///1: OC/OCN are enabled if CCxE/CCxNE are set
387    Enabled = 1,
388}
389impl From<MOE> for bool {
390    #[inline(always)]
391    fn from(variant: MOE) -> Self {
392        variant as u8 != 0
393    }
394}
395///Field `MOE` reader - Main output enable
396pub type MOE_R = crate::BitReader<MOE>;
397impl MOE_R {
398    ///Get enumerated values variant
399    #[inline(always)]
400    pub const fn variant(&self) -> MOE {
401        match self.bits {
402            false => MOE::DisabledIdle,
403            true => MOE::Enabled,
404        }
405    }
406    ///OC/OCN are disabled or forced idle depending on OSSI
407    #[inline(always)]
408    pub fn is_disabled_idle(&self) -> bool {
409        *self == MOE::DisabledIdle
410    }
411    ///OC/OCN are enabled if CCxE/CCxNE are set
412    #[inline(always)]
413    pub fn is_enabled(&self) -> bool {
414        *self == MOE::Enabled
415    }
416}
417///Field `MOE` writer - Main output enable
418pub type MOE_W<'a, REG> = crate::BitWriter<'a, REG, MOE>;
419impl<'a, REG> MOE_W<'a, REG>
420where
421    REG: crate::Writable + crate::RegisterSpec,
422{
423    ///OC/OCN are disabled or forced idle depending on OSSI
424    #[inline(always)]
425    pub fn disabled_idle(self) -> &'a mut crate::W<REG> {
426        self.variant(MOE::DisabledIdle)
427    }
428    ///OC/OCN are enabled if CCxE/CCxNE are set
429    #[inline(always)]
430    pub fn enabled(self) -> &'a mut crate::W<REG> {
431        self.variant(MOE::Enabled)
432    }
433}
434///Field `BKF` reader - Break filter
435pub type BKF_R = crate::FieldReader;
436///Field `BKF` writer - Break filter
437pub type BKF_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
438///Field `BK2F` reader - Break 2 filter
439pub type BK2F_R = crate::FieldReader;
440///Field `BK2F` writer - Break 2 filter
441pub type BK2F_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
442///Field `BK2E` reader - Break 2 enable
443pub use BKE_R as BK2E_R;
444///Field `BK2E` writer - Break 2 enable
445pub use BKE_W as BK2E_W;
446///Field `BK2P` reader - Break 2 polarity
447pub use BKP_R as BK2P_R;
448///Field `BK2P` writer - Break 2 polarity
449pub use BKP_W as BK2P_W;
450impl R {
451    ///Bits 0:7 - Dead-time generator setup
452    #[inline(always)]
453    pub fn dtg(&self) -> DTG_R {
454        DTG_R::new((self.bits & 0xff) as u8)
455    }
456    ///Bits 8:9 - Lock configuration
457    #[inline(always)]
458    pub fn lock(&self) -> LOCK_R {
459        LOCK_R::new(((self.bits >> 8) & 3) as u8)
460    }
461    ///Bit 10 - Off-state selection for Idle mode
462    #[inline(always)]
463    pub fn ossi(&self) -> OSSI_R {
464        OSSI_R::new(((self.bits >> 10) & 1) != 0)
465    }
466    ///Bit 11 - Off-state selection for Run mode
467    #[inline(always)]
468    pub fn ossr(&self) -> OSSR_R {
469        OSSR_R::new(((self.bits >> 11) & 1) != 0)
470    }
471    ///Bit 12 - Break enable
472    #[inline(always)]
473    pub fn bke(&self) -> BKE_R {
474        BKE_R::new(((self.bits >> 12) & 1) != 0)
475    }
476    ///Bit 13 - Break polarity
477    #[inline(always)]
478    pub fn bkp(&self) -> BKP_R {
479        BKP_R::new(((self.bits >> 13) & 1) != 0)
480    }
481    ///Bit 14 - Automatic output enable
482    #[inline(always)]
483    pub fn aoe(&self) -> AOE_R {
484        AOE_R::new(((self.bits >> 14) & 1) != 0)
485    }
486    ///Bit 15 - Main output enable
487    #[inline(always)]
488    pub fn moe(&self) -> MOE_R {
489        MOE_R::new(((self.bits >> 15) & 1) != 0)
490    }
491    ///Bits 16:19 - Break filter
492    #[inline(always)]
493    pub fn bkf(&self) -> BKF_R {
494        BKF_R::new(((self.bits >> 16) & 0x0f) as u8)
495    }
496    ///Bits 20:23 - Break 2 filter
497    #[inline(always)]
498    pub fn bk2f(&self) -> BK2F_R {
499        BK2F_R::new(((self.bits >> 20) & 0x0f) as u8)
500    }
501    ///Bit 24 - Break 2 enable
502    #[inline(always)]
503    pub fn bk2e(&self) -> BK2E_R {
504        BK2E_R::new(((self.bits >> 24) & 1) != 0)
505    }
506    ///Bit 25 - Break 2 polarity
507    #[inline(always)]
508    pub fn bk2p(&self) -> BK2P_R {
509        BK2P_R::new(((self.bits >> 25) & 1) != 0)
510    }
511}
512impl core::fmt::Debug for R {
513    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
514        f.debug_struct("BDTR")
515            .field("bkp", &self.bkp())
516            .field("bk2p", &self.bk2p())
517            .field("bke", &self.bke())
518            .field("bk2e", &self.bk2e())
519            .field("bk2f", &self.bk2f())
520            .field("bkf", &self.bkf())
521            .field("moe", &self.moe())
522            .field("aoe", &self.aoe())
523            .field("ossr", &self.ossr())
524            .field("ossi", &self.ossi())
525            .field("lock", &self.lock())
526            .field("dtg", &self.dtg())
527            .finish()
528    }
529}
530impl W {
531    ///Bits 0:7 - Dead-time generator setup
532    #[inline(always)]
533    pub fn dtg(&mut self) -> DTG_W<BDTRrs> {
534        DTG_W::new(self, 0)
535    }
536    ///Bits 8:9 - Lock configuration
537    #[inline(always)]
538    pub fn lock(&mut self) -> LOCK_W<BDTRrs> {
539        LOCK_W::new(self, 8)
540    }
541    ///Bit 10 - Off-state selection for Idle mode
542    #[inline(always)]
543    pub fn ossi(&mut self) -> OSSI_W<BDTRrs> {
544        OSSI_W::new(self, 10)
545    }
546    ///Bit 11 - Off-state selection for Run mode
547    #[inline(always)]
548    pub fn ossr(&mut self) -> OSSR_W<BDTRrs> {
549        OSSR_W::new(self, 11)
550    }
551    ///Bit 12 - Break enable
552    #[inline(always)]
553    pub fn bke(&mut self) -> BKE_W<BDTRrs> {
554        BKE_W::new(self, 12)
555    }
556    ///Bit 13 - Break polarity
557    #[inline(always)]
558    pub fn bkp(&mut self) -> BKP_W<BDTRrs> {
559        BKP_W::new(self, 13)
560    }
561    ///Bit 14 - Automatic output enable
562    #[inline(always)]
563    pub fn aoe(&mut self) -> AOE_W<BDTRrs> {
564        AOE_W::new(self, 14)
565    }
566    ///Bit 15 - Main output enable
567    #[inline(always)]
568    pub fn moe(&mut self) -> MOE_W<BDTRrs> {
569        MOE_W::new(self, 15)
570    }
571    ///Bits 16:19 - Break filter
572    #[inline(always)]
573    pub fn bkf(&mut self) -> BKF_W<BDTRrs> {
574        BKF_W::new(self, 16)
575    }
576    ///Bits 20:23 - Break 2 filter
577    #[inline(always)]
578    pub fn bk2f(&mut self) -> BK2F_W<BDTRrs> {
579        BK2F_W::new(self, 20)
580    }
581    ///Bit 24 - Break 2 enable
582    #[inline(always)]
583    pub fn bk2e(&mut self) -> BK2E_W<BDTRrs> {
584        BK2E_W::new(self, 24)
585    }
586    ///Bit 25 - Break 2 polarity
587    #[inline(always)]
588    pub fn bk2p(&mut self) -> BK2P_W<BDTRrs> {
589        BK2P_W::new(self, 25)
590    }
591}
592/**break and dead-time register
593
594You can [`read`](crate::Reg::read) this register and get [`bdtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
595
596See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#TIM1:BDTR)*/
597pub struct BDTRrs;
598impl crate::RegisterSpec for BDTRrs {
599    type Ux = u32;
600}
601///`read()` method returns [`bdtr::R`](R) reader structure
602impl crate::Readable for BDTRrs {}
603///`write(|w| ..)` method takes [`bdtr::W`](W) writer structure
604impl crate::Writable for BDTRrs {
605    type Safety = crate::Unsafe;
606}
607///`reset()` method sets BDTR to value 0
608impl crate::Resettable for BDTRrs {}
stm32l4/stm32l4x1/tim1/bdtr.rs

stm32l4/stm32l4x1/tim1/
bdtr.rs
