stm32l4/stm32l4x1/syscfg/
exticr4.rs

1///Register `EXTICR4` reader
2pub type R = crate::R<EXTICR4rs>;
3///Register `EXTICR4` writer
4pub type W = crate::W<EXTICR4rs>;
5///Field `EXTI12` reader - EXTI12 configuration bits
6pub type EXTI12_R = crate::FieldReader;
7///Field `EXTI12` writer - EXTI12 configuration bits
8pub type EXTI12_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9///Field `EXTI13` reader - EXTI13 configuration bits
10pub type EXTI13_R = crate::FieldReader;
11///Field `EXTI13` writer - EXTI13 configuration bits
12pub type EXTI13_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13///Field `EXTI14` reader - EXTI14 configuration bits
14pub type EXTI14_R = crate::FieldReader;
15///Field `EXTI14` writer - EXTI14 configuration bits
16pub type EXTI14_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17///Field `EXTI15` reader - EXTI15 configuration bits
18pub type EXTI15_R = crate::FieldReader;
19///Field `EXTI15` writer - EXTI15 configuration bits
20pub type EXTI15_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21impl R {
22    ///Bits 0:2 - EXTI12 configuration bits
23    #[inline(always)]
24    pub fn exti12(&self) -> EXTI12_R {
25        EXTI12_R::new((self.bits & 7) as u8)
26    }
27    ///Bits 4:6 - EXTI13 configuration bits
28    #[inline(always)]
29    pub fn exti13(&self) -> EXTI13_R {
30        EXTI13_R::new(((self.bits >> 4) & 7) as u8)
31    }
32    ///Bits 8:10 - EXTI14 configuration bits
33    #[inline(always)]
34    pub fn exti14(&self) -> EXTI14_R {
35        EXTI14_R::new(((self.bits >> 8) & 7) as u8)
36    }
37    ///Bits 12:14 - EXTI15 configuration bits
38    #[inline(always)]
39    pub fn exti15(&self) -> EXTI15_R {
40        EXTI15_R::new(((self.bits >> 12) & 7) as u8)
41    }
42}
43impl core::fmt::Debug for R {
44    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
45        f.debug_struct("EXTICR4")
46            .field("exti15", &self.exti15())
47            .field("exti14", &self.exti14())
48            .field("exti13", &self.exti13())
49            .field("exti12", &self.exti12())
50            .finish()
51    }
52}
53impl W {
54    ///Bits 0:2 - EXTI12 configuration bits
55    #[inline(always)]
56    pub fn exti12(&mut self) -> EXTI12_W<EXTICR4rs> {
57        EXTI12_W::new(self, 0)
58    }
59    ///Bits 4:6 - EXTI13 configuration bits
60    #[inline(always)]
61    pub fn exti13(&mut self) -> EXTI13_W<EXTICR4rs> {
62        EXTI13_W::new(self, 4)
63    }
64    ///Bits 8:10 - EXTI14 configuration bits
65    #[inline(always)]
66    pub fn exti14(&mut self) -> EXTI14_W<EXTICR4rs> {
67        EXTI14_W::new(self, 8)
68    }
69    ///Bits 12:14 - EXTI15 configuration bits
70    #[inline(always)]
71    pub fn exti15(&mut self) -> EXTI15_W<EXTICR4rs> {
72        EXTI15_W::new(self, 12)
73    }
74}
75/**external interrupt configuration register 4
76
77You can [`read`](crate::Reg::read) this register and get [`exticr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`exticr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
78
79See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#SYSCFG:EXTICR4)*/
80pub struct EXTICR4rs;
81impl crate::RegisterSpec for EXTICR4rs {
82    type Ux = u32;
83}
84///`read()` method returns [`exticr4::R`](R) reader structure
85impl crate::Readable for EXTICR4rs {}
86///`write(|w| ..)` method takes [`exticr4::W`](W) writer structure
87impl crate::Writable for EXTICR4rs {
88    type Safety = crate::Unsafe;
89}
90///`reset()` method sets EXTICR4 to value 0
91impl crate::Resettable for EXTICR4rs {}
stm32l4/stm32l4x1/syscfg/exticr4.rs

stm32l4/stm32l4x1/syscfg/
exticr4.rs
