stm32l4/stm32l4x1/rcc/
crrcr.rs

1///Register `CRRCR` reader
2pub type R = crate::R<CRRCRrs>;
3///Register `CRRCR` writer
4pub type W = crate::W<CRRCRrs>;
5///Field `HSI48ON` reader - HSI48 clock enable
6pub type HSI48ON_R = crate::BitReader;
7///Field `HSI48ON` writer - HSI48 clock enable
8pub type HSI48ON_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `HSI48RDY` reader - HSI48 clock ready flag
10pub type HSI48RDY_R = crate::BitReader;
11///Field `HSI48CAL` reader - HSI48 clock calibration
12pub type HSI48CAL_R = crate::FieldReader<u16>;
13impl R {
14    ///Bit 0 - HSI48 clock enable
15    #[inline(always)]
16    pub fn hsi48on(&self) -> HSI48ON_R {
17        HSI48ON_R::new((self.bits & 1) != 0)
18    }
19    ///Bit 1 - HSI48 clock ready flag
20    #[inline(always)]
21    pub fn hsi48rdy(&self) -> HSI48RDY_R {
22        HSI48RDY_R::new(((self.bits >> 1) & 1) != 0)
23    }
24    ///Bits 7:15 - HSI48 clock calibration
25    #[inline(always)]
26    pub fn hsi48cal(&self) -> HSI48CAL_R {
27        HSI48CAL_R::new(((self.bits >> 7) & 0x01ff) as u16)
28    }
29}
30impl core::fmt::Debug for R {
31    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
32        f.debug_struct("CRRCR")
33            .field("hsi48on", &self.hsi48on())
34            .field("hsi48rdy", &self.hsi48rdy())
35            .field("hsi48cal", &self.hsi48cal())
36            .finish()
37    }
38}
39impl W {
40    ///Bit 0 - HSI48 clock enable
41    #[inline(always)]
42    pub fn hsi48on(&mut self) -> HSI48ON_W<CRRCRrs> {
43        HSI48ON_W::new(self, 0)
44    }
45}
46/**Clock recovery RC register
47
48You can [`read`](crate::Reg::read) this register and get [`crrcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crrcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
49
50See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#RCC:CRRCR)*/
51pub struct CRRCRrs;
52impl crate::RegisterSpec for CRRCRrs {
53    type Ux = u32;
54}
55///`read()` method returns [`crrcr::R`](R) reader structure
56impl crate::Readable for CRRCRrs {}
57///`write(|w| ..)` method takes [`crrcr::W`](W) writer structure
58impl crate::Writable for CRRCRrs {
59    type Safety = crate::Unsafe;
60}
61///`reset()` method sets CRRCR to value 0x0c00_0600
62impl crate::Resettable for CRRCRrs {
63    const RESET_VALUE: u32 = 0x0c00_0600;
64}
stm32l4/stm32l4x1/rcc/crrcr.rs

stm32l4/stm32l4x1/rcc/
crrcr.rs
