stm32l4/stm32l4x1/rcc/
apb1rstr2.rs

1///Register `APB1RSTR2` reader
2pub type R = crate::R<APB1RSTR2rs>;
3///Register `APB1RSTR2` writer
4pub type W = crate::W<APB1RSTR2rs>;
5///Field `LPUART1RST` reader - Low-power UART 1 reset
6pub type LPUART1RST_R = crate::BitReader;
7///Field `LPUART1RST` writer - Low-power UART 1 reset
8pub type LPUART1RST_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `I2C4RST` reader - I2C4 reset
10pub type I2C4RST_R = crate::BitReader;
11///Field `I2C4RST` writer - I2C4 reset
12pub type I2C4RST_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `SWPMI1RST` reader - Single wire protocol reset
14pub type SWPMI1RST_R = crate::BitReader;
15///Field `SWPMI1RST` writer - Single wire protocol reset
16pub type SWPMI1RST_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `LPTIM2RST` reader - Low-power timer 2 reset
18pub type LPTIM2RST_R = crate::BitReader;
19///Field `LPTIM2RST` writer - Low-power timer 2 reset
20pub type LPTIM2RST_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    ///Bit 0 - Low-power UART 1 reset
23    #[inline(always)]
24    pub fn lpuart1rst(&self) -> LPUART1RST_R {
25        LPUART1RST_R::new((self.bits & 1) != 0)
26    }
27    ///Bit 1 - I2C4 reset
28    #[inline(always)]
29    pub fn i2c4rst(&self) -> I2C4RST_R {
30        I2C4RST_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    ///Bit 2 - Single wire protocol reset
33    #[inline(always)]
34    pub fn swpmi1rst(&self) -> SWPMI1RST_R {
35        SWPMI1RST_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    ///Bit 5 - Low-power timer 2 reset
38    #[inline(always)]
39    pub fn lptim2rst(&self) -> LPTIM2RST_R {
40        LPTIM2RST_R::new(((self.bits >> 5) & 1) != 0)
41    }
42}
43impl core::fmt::Debug for R {
44    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
45        f.debug_struct("APB1RSTR2")
46            .field("lptim2rst", &self.lptim2rst())
47            .field("swpmi1rst", &self.swpmi1rst())
48            .field("lpuart1rst", &self.lpuart1rst())
49            .field("i2c4rst", &self.i2c4rst())
50            .finish()
51    }
52}
53impl W {
54    ///Bit 0 - Low-power UART 1 reset
55    #[inline(always)]
56    pub fn lpuart1rst(&mut self) -> LPUART1RST_W<APB1RSTR2rs> {
57        LPUART1RST_W::new(self, 0)
58    }
59    ///Bit 1 - I2C4 reset
60    #[inline(always)]
61    pub fn i2c4rst(&mut self) -> I2C4RST_W<APB1RSTR2rs> {
62        I2C4RST_W::new(self, 1)
63    }
64    ///Bit 2 - Single wire protocol reset
65    #[inline(always)]
66    pub fn swpmi1rst(&mut self) -> SWPMI1RST_W<APB1RSTR2rs> {
67        SWPMI1RST_W::new(self, 2)
68    }
69    ///Bit 5 - Low-power timer 2 reset
70    #[inline(always)]
71    pub fn lptim2rst(&mut self) -> LPTIM2RST_W<APB1RSTR2rs> {
72        LPTIM2RST_W::new(self, 5)
73    }
74}
75/**APB1 peripheral reset register 2
76
77You can [`read`](crate::Reg::read) this register and get [`apb1rstr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1rstr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
78
79See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#RCC:APB1RSTR2)*/
80pub struct APB1RSTR2rs;
81impl crate::RegisterSpec for APB1RSTR2rs {
82    type Ux = u32;
83}
84///`read()` method returns [`apb1rstr2::R`](R) reader structure
85impl crate::Readable for APB1RSTR2rs {}
86///`write(|w| ..)` method takes [`apb1rstr2::W`](W) writer structure
87impl crate::Writable for APB1RSTR2rs {
88    type Safety = crate::Unsafe;
89}
90///`reset()` method sets APB1RSTR2 to value 0
91impl crate::Resettable for APB1RSTR2rs {}
stm32l4/stm32l4x1/rcc/apb1rstr2.rs

stm32l4/stm32l4x1/rcc/
apb1rstr2.rs
