stm32l4/stm32l4x1/rcc/
ahb2rstr.rs

1///Register `AHB2RSTR` reader
2pub type R = crate::R<AHB2RSTRrs>;
3///Register `AHB2RSTR` writer
4pub type W = crate::W<AHB2RSTRrs>;
5///Field `GPIOARST` reader - IO port A reset
6pub type GPIOARST_R = crate::BitReader;
7///Field `GPIOARST` writer - IO port A reset
8pub type GPIOARST_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `GPIOBRST` reader - IO port B reset
10pub type GPIOBRST_R = crate::BitReader;
11///Field `GPIOBRST` writer - IO port B reset
12pub type GPIOBRST_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `GPIOCRST` reader - IO port C reset
14pub type GPIOCRST_R = crate::BitReader;
15///Field `GPIOCRST` writer - IO port C reset
16pub type GPIOCRST_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `GPIODRST` reader - IO port D reset
18pub type GPIODRST_R = crate::BitReader;
19///Field `GPIODRST` writer - IO port D reset
20pub type GPIODRST_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `GPIOERST` reader - IO port E reset
22pub type GPIOERST_R = crate::BitReader;
23///Field `GPIOERST` writer - IO port E reset
24pub type GPIOERST_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `GPIOHRST` reader - IO port H reset
26pub type GPIOHRST_R = crate::BitReader;
27///Field `GPIOHRST` writer - IO port H reset
28pub type GPIOHRST_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `ADCRST` reader - ADC reset
30pub type ADCRST_R = crate::BitReader;
31///Field `ADCRST` writer - ADC reset
32pub type ADCRST_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `AESRST` reader - AES hardware accelerator reset
34pub type AESRST_R = crate::BitReader;
35///Field `AESRST` writer - AES hardware accelerator reset
36pub type AESRST_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `RNGRST` reader - Random number generator reset
38pub type RNGRST_R = crate::BitReader;
39///Field `RNGRST` writer - Random number generator reset
40pub type RNGRST_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42    ///Bit 0 - IO port A reset
43    #[inline(always)]
44    pub fn gpioarst(&self) -> GPIOARST_R {
45        GPIOARST_R::new((self.bits & 1) != 0)
46    }
47    ///Bit 1 - IO port B reset
48    #[inline(always)]
49    pub fn gpiobrst(&self) -> GPIOBRST_R {
50        GPIOBRST_R::new(((self.bits >> 1) & 1) != 0)
51    }
52    ///Bit 2 - IO port C reset
53    #[inline(always)]
54    pub fn gpiocrst(&self) -> GPIOCRST_R {
55        GPIOCRST_R::new(((self.bits >> 2) & 1) != 0)
56    }
57    ///Bit 3 - IO port D reset
58    #[inline(always)]
59    pub fn gpiodrst(&self) -> GPIODRST_R {
60        GPIODRST_R::new(((self.bits >> 3) & 1) != 0)
61    }
62    ///Bit 4 - IO port E reset
63    #[inline(always)]
64    pub fn gpioerst(&self) -> GPIOERST_R {
65        GPIOERST_R::new(((self.bits >> 4) & 1) != 0)
66    }
67    ///Bit 7 - IO port H reset
68    #[inline(always)]
69    pub fn gpiohrst(&self) -> GPIOHRST_R {
70        GPIOHRST_R::new(((self.bits >> 7) & 1) != 0)
71    }
72    ///Bit 13 - ADC reset
73    #[inline(always)]
74    pub fn adcrst(&self) -> ADCRST_R {
75        ADCRST_R::new(((self.bits >> 13) & 1) != 0)
76    }
77    ///Bit 16 - AES hardware accelerator reset
78    #[inline(always)]
79    pub fn aesrst(&self) -> AESRST_R {
80        AESRST_R::new(((self.bits >> 16) & 1) != 0)
81    }
82    ///Bit 18 - Random number generator reset
83    #[inline(always)]
84    pub fn rngrst(&self) -> RNGRST_R {
85        RNGRST_R::new(((self.bits >> 18) & 1) != 0)
86    }
87}
88impl core::fmt::Debug for R {
89    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
90        f.debug_struct("AHB2RSTR")
91            .field("rngrst", &self.rngrst())
92            .field("aesrst", &self.aesrst())
93            .field("adcrst", &self.adcrst())
94            .field("gpiohrst", &self.gpiohrst())
95            .field("gpioerst", &self.gpioerst())
96            .field("gpiodrst", &self.gpiodrst())
97            .field("gpiocrst", &self.gpiocrst())
98            .field("gpiobrst", &self.gpiobrst())
99            .field("gpioarst", &self.gpioarst())
100            .finish()
101    }
102}
103impl W {
104    ///Bit 0 - IO port A reset
105    #[inline(always)]
106    pub fn gpioarst(&mut self) -> GPIOARST_W<AHB2RSTRrs> {
107        GPIOARST_W::new(self, 0)
108    }
109    ///Bit 1 - IO port B reset
110    #[inline(always)]
111    pub fn gpiobrst(&mut self) -> GPIOBRST_W<AHB2RSTRrs> {
112        GPIOBRST_W::new(self, 1)
113    }
114    ///Bit 2 - IO port C reset
115    #[inline(always)]
116    pub fn gpiocrst(&mut self) -> GPIOCRST_W<AHB2RSTRrs> {
117        GPIOCRST_W::new(self, 2)
118    }
119    ///Bit 3 - IO port D reset
120    #[inline(always)]
121    pub fn gpiodrst(&mut self) -> GPIODRST_W<AHB2RSTRrs> {
122        GPIODRST_W::new(self, 3)
123    }
124    ///Bit 4 - IO port E reset
125    #[inline(always)]
126    pub fn gpioerst(&mut self) -> GPIOERST_W<AHB2RSTRrs> {
127        GPIOERST_W::new(self, 4)
128    }
129    ///Bit 7 - IO port H reset
130    #[inline(always)]
131    pub fn gpiohrst(&mut self) -> GPIOHRST_W<AHB2RSTRrs> {
132        GPIOHRST_W::new(self, 7)
133    }
134    ///Bit 13 - ADC reset
135    #[inline(always)]
136    pub fn adcrst(&mut self) -> ADCRST_W<AHB2RSTRrs> {
137        ADCRST_W::new(self, 13)
138    }
139    ///Bit 16 - AES hardware accelerator reset
140    #[inline(always)]
141    pub fn aesrst(&mut self) -> AESRST_W<AHB2RSTRrs> {
142        AESRST_W::new(self, 16)
143    }
144    ///Bit 18 - Random number generator reset
145    #[inline(always)]
146    pub fn rngrst(&mut self) -> RNGRST_W<AHB2RSTRrs> {
147        RNGRST_W::new(self, 18)
148    }
149}
150/**AHB2 peripheral reset register
151
152You can [`read`](crate::Reg::read) this register and get [`ahb2rstr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb2rstr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
153
154See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#RCC:AHB2RSTR)*/
155pub struct AHB2RSTRrs;
156impl crate::RegisterSpec for AHB2RSTRrs {
157    type Ux = u32;
158}
159///`read()` method returns [`ahb2rstr::R`](R) reader structure
160impl crate::Readable for AHB2RSTRrs {}
161///`write(|w| ..)` method takes [`ahb2rstr::W`](W) writer structure
162impl crate::Writable for AHB2RSTRrs {
163    type Safety = crate::Unsafe;
164}
165///`reset()` method sets AHB2RSTR to value 0
166impl crate::Resettable for AHB2RSTRrs {}
stm32l4/stm32l4x1/rcc/ahb2rstr.rs

stm32l4/stm32l4x1/rcc/
ahb2rstr.rs
