stm32l4/stm32l4x1/
mod.rs

1/*!Peripheral access API for STM32L4X1 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 4;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
16#[cfg(feature = "rt")]
17pub use cortex_m_rt::interrupt;
18#[cfg(feature = "rt")]
19extern "C" {
20    fn WWDG();
21    fn PVD_PVM();
22    fn RTC_TAMP_STAMP();
23    fn RTC_WKUP();
24    fn FLASH();
25    fn RCC();
26    fn EXTI0();
27    fn EXTI1();
28    fn EXTI2();
29    fn EXTI3();
30    fn EXTI4();
31    fn DMA1_CH1();
32    fn DMA1_CH2();
33    fn DMA1_CH3();
34    fn DMA1_CH4();
35    fn DMA1_CH5();
36    fn DMA1_CH6();
37    fn DMA1_CH7();
38    fn ADC1_2();
39    fn CAN1_TX();
40    fn CAN1_RX0();
41    fn CAN1_RX1();
42    fn CAN1_SCE();
43    fn EXTI9_5();
44    fn TIM1_BRK_TIM15();
45    fn TIM1_UP_TIM16();
46    fn TIM1_TRG_COM();
47    fn TIM1_CC();
48    fn TIM2();
49    fn TIM3();
50    fn TIM4();
51    fn I2C1_EV();
52    fn I2C1_ER();
53    fn I2C2_EV();
54    fn I2C2_ER();
55    fn SPI1();
56    fn SPI2();
57    fn USART1();
58    fn USART2();
59    fn USART3();
60    fn EXTI15_10();
61    fn RTC_ALARM();
62    fn DFSDM1_FLT3();
63    fn TIM8_BRK();
64    fn TIM8_UP();
65    fn TIM8_TRG_COM();
66    fn TIM8_CC();
67    fn ADC3();
68    fn SDMMC1();
69    fn TIM5();
70    fn SPI3();
71    fn UART4();
72    fn TIM6_DACUNDER();
73    fn TIM7();
74    fn DMA2_CH1();
75    fn DMA2_CH2();
76    fn DMA2_CH3();
77    fn DMA2_CH4();
78    fn DMA2_CH5();
79    fn DFSDM1_FLT0();
80    fn DFSDM1_FLT1();
81    fn DFSDM1_FLT2();
82    fn COMP();
83    fn LPTIM1();
84    fn LPTIM2();
85    fn USB_FS();
86    fn DMA2_CH6();
87    fn DMA2_CH7();
88    fn LPUART1();
89    fn QUADSPI();
90    fn I2C3_EV();
91    fn I2C3_ER();
92    fn SAI1();
93    fn SWPMI1();
94    fn TSC();
95    fn LCD();
96    fn AES();
97    fn RNG();
98    fn FPU();
99    fn CRS();
100}
101#[doc(hidden)]
102#[repr(C)]
103pub union Vector {
104    _handler: unsafe extern "C" fn(),
105    _reserved: u32,
106}
107#[cfg(feature = "rt")]
108#[doc(hidden)]
109#[link_section = ".vector_table.interrupts"]
110#[no_mangle]
111pub static __INTERRUPTS: [Vector; 83] = [
112    Vector { _handler: WWDG },
113    Vector { _handler: PVD_PVM },
114    Vector {
115        _handler: RTC_TAMP_STAMP,
116    },
117    Vector { _handler: RTC_WKUP },
118    Vector { _handler: FLASH },
119    Vector { _handler: RCC },
120    Vector { _handler: EXTI0 },
121    Vector { _handler: EXTI1 },
122    Vector { _handler: EXTI2 },
123    Vector { _handler: EXTI3 },
124    Vector { _handler: EXTI4 },
125    Vector { _handler: DMA1_CH1 },
126    Vector { _handler: DMA1_CH2 },
127    Vector { _handler: DMA1_CH3 },
128    Vector { _handler: DMA1_CH4 },
129    Vector { _handler: DMA1_CH5 },
130    Vector { _handler: DMA1_CH6 },
131    Vector { _handler: DMA1_CH7 },
132    Vector { _handler: ADC1_2 },
133    Vector { _handler: CAN1_TX },
134    Vector { _handler: CAN1_RX0 },
135    Vector { _handler: CAN1_RX1 },
136    Vector { _handler: CAN1_SCE },
137    Vector { _handler: EXTI9_5 },
138    Vector {
139        _handler: TIM1_BRK_TIM15,
140    },
141    Vector {
142        _handler: TIM1_UP_TIM16,
143    },
144    Vector {
145        _handler: TIM1_TRG_COM,
146    },
147    Vector { _handler: TIM1_CC },
148    Vector { _handler: TIM2 },
149    Vector { _handler: TIM3 },
150    Vector { _handler: TIM4 },
151    Vector { _handler: I2C1_EV },
152    Vector { _handler: I2C1_ER },
153    Vector { _handler: I2C2_EV },
154    Vector { _handler: I2C2_ER },
155    Vector { _handler: SPI1 },
156    Vector { _handler: SPI2 },
157    Vector { _handler: USART1 },
158    Vector { _handler: USART2 },
159    Vector { _handler: USART3 },
160    Vector {
161        _handler: EXTI15_10,
162    },
163    Vector {
164        _handler: RTC_ALARM,
165    },
166    Vector {
167        _handler: DFSDM1_FLT3,
168    },
169    Vector { _handler: TIM8_BRK },
170    Vector { _handler: TIM8_UP },
171    Vector {
172        _handler: TIM8_TRG_COM,
173    },
174    Vector { _handler: TIM8_CC },
175    Vector { _handler: ADC3 },
176    Vector { _reserved: 0 },
177    Vector { _handler: SDMMC1 },
178    Vector { _handler: TIM5 },
179    Vector { _handler: SPI3 },
180    Vector { _handler: UART4 },
181    Vector { _reserved: 0 },
182    Vector {
183        _handler: TIM6_DACUNDER,
184    },
185    Vector { _handler: TIM7 },
186    Vector { _handler: DMA2_CH1 },
187    Vector { _handler: DMA2_CH2 },
188    Vector { _handler: DMA2_CH3 },
189    Vector { _handler: DMA2_CH4 },
190    Vector { _handler: DMA2_CH5 },
191    Vector {
192        _handler: DFSDM1_FLT0,
193    },
194    Vector {
195        _handler: DFSDM1_FLT1,
196    },
197    Vector {
198        _handler: DFSDM1_FLT2,
199    },
200    Vector { _handler: COMP },
201    Vector { _handler: LPTIM1 },
202    Vector { _handler: LPTIM2 },
203    Vector { _handler: USB_FS },
204    Vector { _handler: DMA2_CH6 },
205    Vector { _handler: DMA2_CH7 },
206    Vector { _handler: LPUART1 },
207    Vector { _handler: QUADSPI },
208    Vector { _handler: I2C3_EV },
209    Vector { _handler: I2C3_ER },
210    Vector { _handler: SAI1 },
211    Vector { _reserved: 0 },
212    Vector { _handler: SWPMI1 },
213    Vector { _handler: TSC },
214    Vector { _handler: LCD },
215    Vector { _handler: AES },
216    Vector { _handler: RNG },
217    Vector { _handler: FPU },
218    Vector { _handler: CRS },
219];
220///Enumeration of all the interrupts.
221#[cfg_attr(feature = "defmt", derive(defmt::Format))]
222#[derive(Copy, Clone, Debug, PartialEq, Eq)]
223#[repr(u16)]
224pub enum Interrupt {
225    ///0 - Window Watchdog interrupt
226    WWDG = 0,
227    ///1 - PVD through EXTI line detection
228    PVD_PVM = 1,
229    ///2 - Tamper and TimeStamp interrupts
230    RTC_TAMP_STAMP = 2,
231    ///3 - RTC Tamper or TimeStamp /CSS on LSE through EXTI line 19 interrupts
232    RTC_WKUP = 3,
233    ///4 - Flash global interrupt
234    FLASH = 4,
235    ///5 - RCC global interrupt
236    RCC = 5,
237    ///6 - EXTI Line 0 interrupt
238    EXTI0 = 6,
239    ///7 - EXTI Line 1 interrupt
240    EXTI1 = 7,
241    ///8 - EXTI Line 2 interrupt
242    EXTI2 = 8,
243    ///9 - EXTI Line 3 interrupt
244    EXTI3 = 9,
245    ///10 - EXTI Line4 interrupt
246    EXTI4 = 10,
247    ///11 - DMA1 Channel1 global interrupt
248    DMA1_CH1 = 11,
249    ///12 - DMA1 Channel2 global interrupt
250    DMA1_CH2 = 12,
251    ///13 - DMA1 Channel3 interrupt
252    DMA1_CH3 = 13,
253    ///14 - DMA1 Channel4 interrupt
254    DMA1_CH4 = 14,
255    ///15 - DMA1 Channel5 interrupt
256    DMA1_CH5 = 15,
257    ///16 - DMA1 Channel6 interrupt
258    DMA1_CH6 = 16,
259    ///17 - DMA1 Channel 7 interrupt
260    DMA1_CH7 = 17,
261    ///18 - ADC1 and ADC2 global interrupt
262    ADC1_2 = 18,
263    ///19 - CAN1 TX interrupts
264    CAN1_TX = 19,
265    ///20 - CAN1 RX0 interrupts
266    CAN1_RX0 = 20,
267    ///21 - CAN1 RX1 interrupts
268    CAN1_RX1 = 21,
269    ///22 - CAN1 SCE interrupt
270    CAN1_SCE = 22,
271    ///23 - EXTI Line5 to Line9 interrupts
272    EXTI9_5 = 23,
273    ///24 - TIM1 Break/TIM15 global interrupts
274    TIM1_BRK_TIM15 = 24,
275    ///25 - TIM1 Update/TIM16 global interrupts
276    TIM1_UP_TIM16 = 25,
277    ///26 - TIM1 trigger and commutation interrupt
278    TIM1_TRG_COM = 26,
279    ///27 - TIM1 Capture Compare interrupt
280    TIM1_CC = 27,
281    ///28 - TIM2 global interrupt
282    TIM2 = 28,
283    ///29 - TIM3 global interrupt
284    TIM3 = 29,
285    ///30 - TIM4 global interrupt
286    TIM4 = 30,
287    ///31 - I2C1 event interrupt
288    I2C1_EV = 31,
289    ///32 - I2C1 error interrupt
290    I2C1_ER = 32,
291    ///33 - I2C2 event interrupt
292    I2C2_EV = 33,
293    ///34 - I2C2 error interrupt
294    I2C2_ER = 34,
295    ///35 - SPI1 global interrupt
296    SPI1 = 35,
297    ///36 - SPI2 global interrupt
298    SPI2 = 36,
299    ///37 - USART1 global interrupt
300    USART1 = 37,
301    ///38 - USART2 global interrupt
302    USART2 = 38,
303    ///39 - USART3 global interrupt
304    USART3 = 39,
305    ///40 - EXTI Lines 10 to 15 interrupts
306    EXTI15_10 = 40,
307    ///41 - RTC alarms through EXTI line 18 interrupts
308    RTC_ALARM = 41,
309    ///42 - DFSDM1_FLT3 global interrupt
310    DFSDM1_FLT3 = 42,
311    ///43 - TIM8 Break interrupt
312    TIM8_BRK = 43,
313    ///44 - TIM8 Update interrupt
314    TIM8_UP = 44,
315    ///45 - TIM8 trigger and commutation interrupt
316    TIM8_TRG_COM = 45,
317    ///46 - TIM8 capture compare interrupt
318    TIM8_CC = 46,
319    ///47 - ADC3 global Interrupt
320    ADC3 = 47,
321    ///49 - SDMMC global Interrupt
322    SDMMC1 = 49,
323    ///50 - TIM5 global interrupt
324    TIM5 = 50,
325    ///51 - SPI3 global Interrupt
326    SPI3 = 51,
327    ///52 - UART4 global Interrupt
328    UART4 = 52,
329    ///54 - TIM6 global and DAC12 underrun interrupts
330    TIM6_DACUNDER = 54,
331    ///55 - TIM7 global interrupt
332    TIM7 = 55,
333    ///56 - DMA2 Channel 1 global Interrupt
334    DMA2_CH1 = 56,
335    ///57 - DMA2 Channel 2 global Interrupt
336    DMA2_CH2 = 57,
337    ///58 - DMA2 Channel 3 global Interrupt
338    DMA2_CH3 = 58,
339    ///59 - DMA2 Channel 4 global Interrupt
340    DMA2_CH4 = 59,
341    ///60 - DMA2 Channel 5 global Interrupt
342    DMA2_CH5 = 60,
343    ///61 - DFSDM1_FLT0 global interrupt
344    DFSDM1_FLT0 = 61,
345    ///62 - DFSDM1_FLT1 global interrupt
346    DFSDM1_FLT1 = 62,
347    ///63 - DFSDM1_FLT2 global interrupt
348    DFSDM1_FLT2 = 63,
349    ///64 - COMP1 and COMP2 interrupts
350    COMP = 64,
351    ///65 - LP TIM1 interrupt
352    LPTIM1 = 65,
353    ///66 - LP TIM2 interrupt
354    LPTIM2 = 66,
355    ///67 - USB event interrupt through EXTI
356    USB_FS = 67,
357    ///68 - DMA2 Channel 6 global Interrupt
358    DMA2_CH6 = 68,
359    ///69 - DMA2 Channel 7 global Interrupt
360    DMA2_CH7 = 69,
361    ///70 - LPUART1 global interrupt
362    LPUART1 = 70,
363    ///71 - Quad SPI global interrupt
364    QUADSPI = 71,
365    ///72 - I2C3 event interrupt
366    I2C3_EV = 72,
367    ///73 - I2C3 error interrupt
368    I2C3_ER = 73,
369    ///74 - SAI1 global interrupt
370    SAI1 = 74,
371    ///76 - SWPMI1 global interrupt
372    SWPMI1 = 76,
373    ///77 - TSC global interrupt
374    TSC = 77,
375    ///78 - LCD global interrupt
376    LCD = 78,
377    ///79 - AES global interrupt
378    AES = 79,
379    ///80 - RNG global interrupt
380    RNG = 80,
381    ///81 - Floating point unit interrupt
382    FPU = 81,
383    ///82 - CRS interrupt
384    CRS = 82,
385}
386unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
387    #[inline(always)]
388    fn number(self) -> u16 {
389        self as u16
390    }
391}
392///Digital-to-analog converter
393///
394///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#DAC)
395pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
396impl core::fmt::Debug for DAC {
397    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
398        f.debug_struct("DAC").finish()
399    }
400}
401///Digital-to-analog converter
402pub mod dac;
403///Direct memory access controller
404///
405///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#DMA1)
406pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
407impl core::fmt::Debug for DMA1 {
408    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
409        f.debug_struct("DMA1").finish()
410    }
411}
412///Direct memory access controller
413pub mod dma1;
414///Direct memory access controller
415///
416///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#DMA1)
417pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
418impl core::fmt::Debug for DMA2 {
419    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
420        f.debug_struct("DMA2").finish()
421    }
422}
423///Direct memory access controller
424pub use self::dma1 as dma2;
425///Cyclic redundancy check calculation unit
426///
427///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#CRC)
428pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
429impl core::fmt::Debug for CRC {
430    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
431        f.debug_struct("CRC").finish()
432    }
433}
434///Cyclic redundancy check calculation unit
435pub mod crc;
436///Liquid crystal display controller
437///
438///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#LCD)
439pub type LCD = crate::Periph<lcd::RegisterBlock, 0x4000_2400>;
440impl core::fmt::Debug for LCD {
441    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
442        f.debug_struct("LCD").finish()
443    }
444}
445///Liquid crystal display controller
446pub mod lcd;
447///Touch sensing controller
448///
449///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#TSC)
450pub type TSC = crate::Periph<tsc::RegisterBlock, 0x4002_4000>;
451impl core::fmt::Debug for TSC {
452    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
453        f.debug_struct("TSC").finish()
454    }
455}
456///Touch sensing controller
457pub mod tsc;
458///Independent watchdog
459///
460///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#IWDG)
461pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
462impl core::fmt::Debug for IWDG {
463    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
464        f.debug_struct("IWDG").finish()
465    }
466}
467///Independent watchdog
468pub mod iwdg;
469///System window watchdog
470///
471///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#WWDG)
472pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
473impl core::fmt::Debug for WWDG {
474    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
475        f.debug_struct("WWDG").finish()
476    }
477}
478///System window watchdog
479pub mod wwdg;
480///Comparator
481///
482///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#COMP)
483pub type COMP = crate::Periph<comp::RegisterBlock, 0x4001_0200>;
484impl core::fmt::Debug for COMP {
485    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
486        f.debug_struct("COMP").finish()
487    }
488}
489///Comparator
490pub mod comp;
491///Firewall
492///
493///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#FIREWALL)
494pub type FIREWALL = crate::Periph<firewall::RegisterBlock, 0x4001_1c00>;
495impl core::fmt::Debug for FIREWALL {
496    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
497        f.debug_struct("FIREWALL").finish()
498    }
499}
500///Firewall
501pub mod firewall;
502///Inter-integrated circuit
503///
504///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#I2C1)
505pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
506impl core::fmt::Debug for I2C1 {
507    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
508        f.debug_struct("I2C1").finish()
509    }
510}
511///Inter-integrated circuit
512pub mod i2c1;
513///Inter-integrated circuit
514///
515///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#I2C1)
516pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_5c00>;
517impl core::fmt::Debug for I2C3 {
518    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
519        f.debug_struct("I2C3").finish()
520    }
521}
522///Inter-integrated circuit
523pub use self::i2c1 as i2c3;
524///Inter-integrated circuit
525///
526///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#I2C1)
527pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
528impl core::fmt::Debug for I2C2 {
529    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
530        f.debug_struct("I2C2").finish()
531    }
532}
533///Inter-integrated circuit
534pub use self::i2c1 as i2c2;
535///Flash
536///
537///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#FLASH)
538pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
539impl core::fmt::Debug for FLASH {
540    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
541        f.debug_struct("FLASH").finish()
542    }
543}
544///Flash
545pub mod flash;
546///Reset and clock control
547///
548///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#RCC)
549pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
550impl core::fmt::Debug for RCC {
551    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
552        f.debug_struct("RCC").finish()
553    }
554}
555///Reset and clock control
556pub mod rcc;
557///Power control
558///
559///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#PWR)
560pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
561impl core::fmt::Debug for PWR {
562    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
563        f.debug_struct("PWR").finish()
564    }
565}
566///Power control
567pub mod pwr;
568///System configuration controller
569///
570///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#SYSCFG)
571pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_0000>;
572impl core::fmt::Debug for SYSCFG {
573    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
574        f.debug_struct("SYSCFG").finish()
575    }
576}
577///System configuration controller
578pub mod syscfg;
579///Random number generator
580///
581///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#RNG)
582pub type RNG = crate::Periph<rng::RegisterBlock, 0x5006_0800>;
583impl core::fmt::Debug for RNG {
584    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
585        f.debug_struct("RNG").finish()
586    }
587}
588///Random number generator
589pub mod rng;
590///Advanced encryption standard hardware accelerator
591///
592///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#AES)
593pub type AES = crate::Periph<aes::RegisterBlock, 0x5006_0000>;
594impl core::fmt::Debug for AES {
595    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
596        f.debug_struct("AES").finish()
597    }
598}
599///Advanced encryption standard hardware accelerator
600pub mod aes;
601///Analog-to-Digital Converter
602///
603///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#ADC1)
604pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x5004_0000>;
605impl core::fmt::Debug for ADC1 {
606    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
607        f.debug_struct("ADC1").finish()
608    }
609}
610///Analog-to-Digital Converter
611pub mod adc1;
612///Analog-to-Digital Converter
613///
614///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#ADC1)
615pub type ADC2 = crate::Periph<adc1::RegisterBlock, 0x5004_0100>;
616impl core::fmt::Debug for ADC2 {
617    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
618        f.debug_struct("ADC2").finish()
619    }
620}
621///Analog-to-Digital Converter
622pub use self::adc1 as adc2;
623///Analog-to-Digital Converter
624///
625///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#ADC1)
626pub type ADC3 = crate::Periph<adc1::RegisterBlock, 0x5004_0200>;
627impl core::fmt::Debug for ADC3 {
628    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
629        f.debug_struct("ADC3").finish()
630    }
631}
632///Analog-to-Digital Converter
633pub use self::adc1 as adc3;
634///Analog-to-Digital Converter
635///
636///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#ADC123_Common)
637pub type ADC123_COMMON = crate::Periph<adc123_common::RegisterBlock, 0x5004_0300>;
638impl core::fmt::Debug for ADC123_COMMON {
639    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
640        f.debug_struct("ADC123_COMMON").finish()
641    }
642}
643///Analog-to-Digital Converter
644pub mod adc123_common;
645///ADC common registers
646///
647///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#ADC_Common)
648pub type ADC_COMMON = crate::Periph<adc_common::RegisterBlock, 0x5004_0300>;
649impl core::fmt::Debug for ADC_COMMON {
650    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
651        f.debug_struct("ADC_COMMON").finish()
652    }
653}
654///ADC common registers
655pub mod adc_common;
656///General-purpose I/Os
657///
658///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#GPIOA)
659pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4800_0000>;
660impl core::fmt::Debug for GPIOA {
661    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
662        f.debug_struct("GPIOA").finish()
663    }
664}
665///General-purpose I/Os
666pub mod gpioa;
667///General-purpose I/Os
668///
669///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#GPIOB)
670pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4800_0400>;
671impl core::fmt::Debug for GPIOB {
672    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
673        f.debug_struct("GPIOB").finish()
674    }
675}
676///General-purpose I/Os
677pub mod gpiob;
678///General-purpose I/Os
679///
680///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#GPIOC)
681pub type GPIOC = crate::Periph<gpioc::RegisterBlock, 0x4800_0800>;
682impl core::fmt::Debug for GPIOC {
683    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
684        f.debug_struct("GPIOC").finish()
685    }
686}
687///General-purpose I/Os
688pub mod gpioc;
689///General-purpose I/Os
690///
691///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#GPIOC)
692pub type GPIOD = crate::Periph<gpioc::RegisterBlock, 0x4800_0c00>;
693impl core::fmt::Debug for GPIOD {
694    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
695        f.debug_struct("GPIOD").finish()
696    }
697}
698///General-purpose I/Os
699pub use self::gpioc as gpiod;
700///General-purpose I/Os
701///
702///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#GPIOC)
703pub type GPIOE = crate::Periph<gpioc::RegisterBlock, 0x4800_1000>;
704impl core::fmt::Debug for GPIOE {
705    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
706        f.debug_struct("GPIOE").finish()
707    }
708}
709///General-purpose I/Os
710pub use self::gpioc as gpioe;
711///General-purpose I/Os
712///
713///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#GPIOC)
714pub type GPIOF = crate::Periph<gpioc::RegisterBlock, 0x4800_1400>;
715impl core::fmt::Debug for GPIOF {
716    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
717        f.debug_struct("GPIOF").finish()
718    }
719}
720///General-purpose I/Os
721pub use self::gpioc as gpiof;
722///General-purpose I/Os
723///
724///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#GPIOC)
725pub type GPIOG = crate::Periph<gpioc::RegisterBlock, 0x4800_1800>;
726impl core::fmt::Debug for GPIOG {
727    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
728        f.debug_struct("GPIOG").finish()
729    }
730}
731///General-purpose I/Os
732pub use self::gpioc as gpiog;
733///General-purpose I/Os
734///
735///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#GPIOC)
736pub type GPIOH = crate::Periph<gpioc::RegisterBlock, 0x4800_1c00>;
737impl core::fmt::Debug for GPIOH {
738    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
739        f.debug_struct("GPIOH").finish()
740    }
741}
742///General-purpose I/Os
743pub use self::gpioc as gpioh;
744///Serial audio interface
745///
746///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#SAI1)
747pub type SAI1 = crate::Periph<sai1::RegisterBlock, 0x4001_5400>;
748impl core::fmt::Debug for SAI1 {
749    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
750        f.debug_struct("SAI1").finish()
751    }
752}
753///Serial audio interface
754pub mod sai1;
755///General-purpose-timers
756///
757///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#TIM2)
758pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
759impl core::fmt::Debug for TIM2 {
760    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
761        f.debug_struct("TIM2").finish()
762    }
763}
764///General-purpose-timers
765pub mod tim2;
766///General-purpose-timers
767///
768///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#TIM3)
769pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_0400>;
770impl core::fmt::Debug for TIM3 {
771    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
772        f.debug_struct("TIM3").finish()
773    }
774}
775///General-purpose-timers
776pub mod tim3;
777///General-purpose-timers
778///
779///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#TIM3)
780pub type TIM4 = crate::Periph<tim3::RegisterBlock, 0x4000_0800>;
781impl core::fmt::Debug for TIM4 {
782    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
783        f.debug_struct("TIM4").finish()
784    }
785}
786///General-purpose-timers
787pub use self::tim3 as tim4;
788///General-purpose-timers
789///
790///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#TIM3)
791pub type TIM5 = crate::Periph<tim3::RegisterBlock, 0x4000_0c00>;
792impl core::fmt::Debug for TIM5 {
793    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
794        f.debug_struct("TIM5").finish()
795    }
796}
797///General-purpose-timers
798pub use self::tim3 as tim5;
799///General purpose timers
800///
801///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#TIM15)
802pub type TIM15 = crate::Periph<tim15::RegisterBlock, 0x4001_4000>;
803impl core::fmt::Debug for TIM15 {
804    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
805        f.debug_struct("TIM15").finish()
806    }
807}
808///General purpose timers
809pub mod tim15;
810///General purpose timers
811///
812///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#TIM16)
813pub type TIM16 = crate::Periph<tim16::RegisterBlock, 0x4001_4400>;
814impl core::fmt::Debug for TIM16 {
815    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
816        f.debug_struct("TIM16").finish()
817    }
818}
819///General purpose timers
820pub mod tim16;
821///General purpose timers
822///
823///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#TIM16)
824pub type TIM17 = crate::Periph<tim16::RegisterBlock, 0x4001_4800>;
825impl core::fmt::Debug for TIM17 {
826    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
827        f.debug_struct("TIM17").finish()
828    }
829}
830///General purpose timers
831pub use self::tim16 as tim17;
832///Advanced-timers
833///
834///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#TIM1)
835pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_2c00>;
836impl core::fmt::Debug for TIM1 {
837    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
838        f.debug_struct("TIM1").finish()
839    }
840}
841///Advanced-timers
842pub mod tim1;
843///Advanced-timers
844///
845///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#TIM8)
846pub type TIM8 = crate::Periph<tim8::RegisterBlock, 0x4001_3400>;
847impl core::fmt::Debug for TIM8 {
848    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
849        f.debug_struct("TIM8").finish()
850    }
851}
852///Advanced-timers
853pub mod tim8;
854///Basic-timers
855///
856///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#TIM6)
857pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
858impl core::fmt::Debug for TIM6 {
859    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
860        f.debug_struct("TIM6").finish()
861    }
862}
863///Basic-timers
864pub mod tim6;
865///Basic-timers
866///
867///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#TIM6)
868pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
869impl core::fmt::Debug for TIM7 {
870    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
871        f.debug_struct("TIM7").finish()
872    }
873}
874///Basic-timers
875pub use self::tim6 as tim7;
876///Low power timer
877///
878///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#LPTIM1)
879pub type LPTIM1 = crate::Periph<lptim1::RegisterBlock, 0x4000_7c00>;
880impl core::fmt::Debug for LPTIM1 {
881    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
882        f.debug_struct("LPTIM1").finish()
883    }
884}
885///Low power timer
886pub mod lptim1;
887///Low power timer
888///
889///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#LPTIM1)
890pub type LPTIM2 = crate::Periph<lptim1::RegisterBlock, 0x4000_9400>;
891impl core::fmt::Debug for LPTIM2 {
892    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
893        f.debug_struct("LPTIM2").finish()
894    }
895}
896///Low power timer
897pub use self::lptim1 as lptim2;
898///Universal synchronous asynchronous receiver transmitter
899///
900///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#USART1)
901pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
902impl core::fmt::Debug for USART1 {
903    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
904        f.debug_struct("USART1").finish()
905    }
906}
907///Universal synchronous asynchronous receiver transmitter
908pub mod usart1;
909///Universal synchronous asynchronous receiver transmitter
910///
911///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#USART1)
912pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
913impl core::fmt::Debug for USART2 {
914    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
915        f.debug_struct("USART2").finish()
916    }
917}
918///Universal synchronous asynchronous receiver transmitter
919pub use self::usart1 as usart2;
920///Universal synchronous asynchronous receiver transmitter
921///
922///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#USART1)
923pub type UART4 = crate::Periph<usart1::RegisterBlock, 0x4000_4c00>;
924impl core::fmt::Debug for UART4 {
925    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
926        f.debug_struct("UART4").finish()
927    }
928}
929///Universal synchronous asynchronous receiver transmitter
930pub use self::usart1 as uart4;
931///Universal synchronous asynchronous receiver transmitter
932///
933///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#USART1)
934pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
935impl core::fmt::Debug for USART3 {
936    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
937        f.debug_struct("USART3").finish()
938    }
939}
940///Universal synchronous asynchronous receiver transmitter
941pub use self::usart1 as usart3;
942///Universal synchronous asynchronous receiver transmitter
943///
944///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#LPUART1)
945pub type LPUART1 = crate::Periph<lpuart1::RegisterBlock, 0x4000_8000>;
946impl core::fmt::Debug for LPUART1 {
947    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
948        f.debug_struct("LPUART1").finish()
949    }
950}
951///Universal synchronous asynchronous receiver transmitter
952pub mod lpuart1;
953///Serial peripheral interface/Inter-IC sound
954///
955///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#SPI1)
956pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
957impl core::fmt::Debug for SPI1 {
958    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
959        f.debug_struct("SPI1").finish()
960    }
961}
962///Serial peripheral interface/Inter-IC sound
963pub mod spi1;
964///Serial peripheral interface/Inter-IC sound
965///
966///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#SPI1)
967pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
968impl core::fmt::Debug for SPI3 {
969    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
970        f.debug_struct("SPI3").finish()
971    }
972}
973///Serial peripheral interface/Inter-IC sound
974pub use self::spi1 as spi3;
975///Serial peripheral interface/Inter-IC sound
976///
977///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#SPI1)
978pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
979impl core::fmt::Debug for SPI2 {
980    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
981        f.debug_struct("SPI2").finish()
982    }
983}
984///Serial peripheral interface/Inter-IC sound
985pub use self::spi1 as spi2;
986///Secure digital input/output interface
987///
988///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#SDMMC)
989pub type SDMMC = crate::Periph<sdmmc::RegisterBlock, 0x4001_2800>;
990impl core::fmt::Debug for SDMMC {
991    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
992        f.debug_struct("SDMMC").finish()
993    }
994}
995///Secure digital input/output interface
996pub mod sdmmc;
997///External interrupt/event controller
998///
999///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#EXTI)
1000pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
1001impl core::fmt::Debug for EXTI {
1002    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1003        f.debug_struct("EXTI").finish()
1004    }
1005}
1006///External interrupt/event controller
1007pub mod exti;
1008///Voltage reference buffer
1009///
1010///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#VREFBUF)
1011pub type VREFBUF = crate::Periph<vrefbuf::RegisterBlock, 0x4001_0030>;
1012impl core::fmt::Debug for VREFBUF {
1013    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1014        f.debug_struct("VREFBUF").finish()
1015    }
1016}
1017///Voltage reference buffer
1018pub mod vrefbuf;
1019///Controller area network
1020///
1021///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#CAN1)
1022pub type CAN1 = crate::Periph<can1::RegisterBlock, 0x4000_6400>;
1023impl core::fmt::Debug for CAN1 {
1024    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1025        f.debug_struct("CAN1").finish()
1026    }
1027}
1028///Controller area network
1029pub mod can1;
1030///Real-time clock
1031///
1032///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#RTC)
1033pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
1034impl core::fmt::Debug for RTC {
1035    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1036        f.debug_struct("RTC").finish()
1037    }
1038}
1039///Real-time clock
1040pub mod rtc;
1041///Single Wire Protocol Master Interface
1042///
1043///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#SWPMI1)
1044pub type SWPMI1 = crate::Periph<swpmi1::RegisterBlock, 0x4000_8800>;
1045impl core::fmt::Debug for SWPMI1 {
1046    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1047        f.debug_struct("SWPMI1").finish()
1048    }
1049}
1050///Single Wire Protocol Master Interface
1051pub mod swpmi1;
1052///Operational amplifiers
1053///
1054///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#OPAMP)
1055pub type OPAMP = crate::Periph<opamp::RegisterBlock, 0x4000_7800>;
1056impl core::fmt::Debug for OPAMP {
1057    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1058        f.debug_struct("OPAMP").finish()
1059    }
1060}
1061///Operational amplifiers
1062pub mod opamp;
1063///Clock recovery system
1064///
1065///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#CRS)
1066pub type CRS = crate::Periph<crs::RegisterBlock, 0x4000_6000>;
1067impl core::fmt::Debug for CRS {
1068    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1069        f.debug_struct("CRS").finish()
1070    }
1071}
1072///Clock recovery system
1073pub mod crs;
1074///Universal serial bus full-speed device interface
1075///
1076///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#USB_SRAM)
1077pub type USB_SRAM = crate::Periph<usb_sram::RegisterBlock, 0x4000_6c00>;
1078impl core::fmt::Debug for USB_SRAM {
1079    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1080        f.debug_struct("USB_SRAM").finish()
1081    }
1082}
1083///Universal serial bus full-speed device interface
1084pub mod usb_sram;
1085///Universal serial bus full-speed device interface
1086///
1087///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#USB_SRAM)
1088pub type USB_FS = crate::Periph<usb_sram::RegisterBlock, 0x4000_6800>;
1089impl core::fmt::Debug for USB_FS {
1090    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1091        f.debug_struct("USB_FS").finish()
1092    }
1093}
1094///Universal serial bus full-speed device interface
1095pub use self::usb_sram as usb_fs;
1096///Digital filter for sigma delta modulators
1097///
1098///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#DFSDM)
1099pub type DFSDM = crate::Periph<dfsdm::RegisterBlock, 0x4001_6000>;
1100impl core::fmt::Debug for DFSDM {
1101    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1102        f.debug_struct("DFSDM").finish()
1103    }
1104}
1105///Digital filter for sigma delta modulators
1106pub mod dfsdm;
1107///QuadSPI interface
1108///
1109///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#QUADSPI)
1110pub type QUADSPI = crate::Periph<quadspi::RegisterBlock, 0xa000_1000>;
1111impl core::fmt::Debug for QUADSPI {
1112    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1113        f.debug_struct("QUADSPI").finish()
1114    }
1115}
1116///QuadSPI interface
1117pub mod quadspi;
1118///MCU debug component
1119///
1120///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#DBGMCU)
1121pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
1122impl core::fmt::Debug for DBGMCU {
1123    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1124        f.debug_struct("DBGMCU").finish()
1125    }
1126}
1127///MCU debug component
1128pub mod dbgmcu;
1129#[no_mangle]
1130static mut DEVICE_PERIPHERALS: bool = false;
1131/// All the peripherals.
1132#[allow(non_snake_case)]
1133pub struct Peripherals {
1134    ///DAC
1135    pub DAC: DAC,
1136    ///DMA1
1137    pub DMA1: DMA1,
1138    ///DMA2
1139    pub DMA2: DMA2,
1140    ///CRC
1141    pub CRC: CRC,
1142    ///LCD
1143    pub LCD: LCD,
1144    ///TSC
1145    pub TSC: TSC,
1146    ///IWDG
1147    pub IWDG: IWDG,
1148    ///WWDG
1149    pub WWDG: WWDG,
1150    ///COMP
1151    pub COMP: COMP,
1152    ///FIREWALL
1153    pub FIREWALL: FIREWALL,
1154    ///I2C1
1155    pub I2C1: I2C1,
1156    ///I2C3
1157    pub I2C3: I2C3,
1158    ///I2C2
1159    pub I2C2: I2C2,
1160    ///FLASH
1161    pub FLASH: FLASH,
1162    ///RCC
1163    pub RCC: RCC,
1164    ///PWR
1165    pub PWR: PWR,
1166    ///SYSCFG
1167    pub SYSCFG: SYSCFG,
1168    ///RNG
1169    pub RNG: RNG,
1170    ///AES
1171    pub AES: AES,
1172    ///ADC1
1173    pub ADC1: ADC1,
1174    ///ADC2
1175    pub ADC2: ADC2,
1176    ///ADC3
1177    pub ADC3: ADC3,
1178    ///ADC123_Common
1179    pub ADC123_COMMON: ADC123_COMMON,
1180    ///ADC_Common
1181    pub ADC_COMMON: ADC_COMMON,
1182    ///GPIOA
1183    pub GPIOA: GPIOA,
1184    ///GPIOB
1185    pub GPIOB: GPIOB,
1186    ///GPIOC
1187    pub GPIOC: GPIOC,
1188    ///GPIOD
1189    pub GPIOD: GPIOD,
1190    ///GPIOE
1191    pub GPIOE: GPIOE,
1192    ///GPIOF
1193    pub GPIOF: GPIOF,
1194    ///GPIOG
1195    pub GPIOG: GPIOG,
1196    ///GPIOH
1197    pub GPIOH: GPIOH,
1198    ///SAI1
1199    pub SAI1: SAI1,
1200    ///TIM2
1201    pub TIM2: TIM2,
1202    ///TIM3
1203    pub TIM3: TIM3,
1204    ///TIM4
1205    pub TIM4: TIM4,
1206    ///TIM5
1207    pub TIM5: TIM5,
1208    ///TIM15
1209    pub TIM15: TIM15,
1210    ///TIM16
1211    pub TIM16: TIM16,
1212    ///TIM17
1213    pub TIM17: TIM17,
1214    ///TIM1
1215    pub TIM1: TIM1,
1216    ///TIM8
1217    pub TIM8: TIM8,
1218    ///TIM6
1219    pub TIM6: TIM6,
1220    ///TIM7
1221    pub TIM7: TIM7,
1222    ///LPTIM1
1223    pub LPTIM1: LPTIM1,
1224    ///LPTIM2
1225    pub LPTIM2: LPTIM2,
1226    ///USART1
1227    pub USART1: USART1,
1228    ///USART2
1229    pub USART2: USART2,
1230    ///UART4
1231    pub UART4: UART4,
1232    ///USART3
1233    pub USART3: USART3,
1234    ///LPUART1
1235    pub LPUART1: LPUART1,
1236    ///SPI1
1237    pub SPI1: SPI1,
1238    ///SPI3
1239    pub SPI3: SPI3,
1240    ///SPI2
1241    pub SPI2: SPI2,
1242    ///SDMMC
1243    pub SDMMC: SDMMC,
1244    ///EXTI
1245    pub EXTI: EXTI,
1246    ///VREFBUF
1247    pub VREFBUF: VREFBUF,
1248    ///CAN1
1249    pub CAN1: CAN1,
1250    ///RTC
1251    pub RTC: RTC,
1252    ///SWPMI1
1253    pub SWPMI1: SWPMI1,
1254    ///OPAMP
1255    pub OPAMP: OPAMP,
1256    ///CRS
1257    pub CRS: CRS,
1258    ///USB_SRAM
1259    pub USB_SRAM: USB_SRAM,
1260    ///USB_FS
1261    pub USB_FS: USB_FS,
1262    ///DFSDM
1263    pub DFSDM: DFSDM,
1264    ///QUADSPI
1265    pub QUADSPI: QUADSPI,
1266    ///DBGMCU
1267    pub DBGMCU: DBGMCU,
1268}
1269impl Peripherals {
1270    /// Returns all the peripherals *once*.
1271    #[cfg(feature = "critical-section")]
1272    #[inline]
1273    pub fn take() -> Option<Self> {
1274        critical_section::with(|_| {
1275            if unsafe { DEVICE_PERIPHERALS } {
1276                return None;
1277            }
1278            Some(unsafe { Peripherals::steal() })
1279        })
1280    }
1281    /// Unchecked version of `Peripherals::take`.
1282    ///
1283    /// # Safety
1284    ///
1285    /// Each of the returned peripherals must be used at most once.
1286    #[inline]
1287    pub unsafe fn steal() -> Self {
1288        DEVICE_PERIPHERALS = true;
1289        Peripherals {
1290            DAC: DAC::steal(),
1291            DMA1: DMA1::steal(),
1292            DMA2: DMA2::steal(),
1293            CRC: CRC::steal(),
1294            LCD: LCD::steal(),
1295            TSC: TSC::steal(),
1296            IWDG: IWDG::steal(),
1297            WWDG: WWDG::steal(),
1298            COMP: COMP::steal(),
1299            FIREWALL: FIREWALL::steal(),
1300            I2C1: I2C1::steal(),
1301            I2C3: I2C3::steal(),
1302            I2C2: I2C2::steal(),
1303            FLASH: FLASH::steal(),
1304            RCC: RCC::steal(),
1305            PWR: PWR::steal(),
1306            SYSCFG: SYSCFG::steal(),
1307            RNG: RNG::steal(),
1308            AES: AES::steal(),
1309            ADC1: ADC1::steal(),
1310            ADC2: ADC2::steal(),
1311            ADC3: ADC3::steal(),
1312            ADC123_COMMON: ADC123_COMMON::steal(),
1313            ADC_COMMON: ADC_COMMON::steal(),
1314            GPIOA: GPIOA::steal(),
1315            GPIOB: GPIOB::steal(),
1316            GPIOC: GPIOC::steal(),
1317            GPIOD: GPIOD::steal(),
1318            GPIOE: GPIOE::steal(),
1319            GPIOF: GPIOF::steal(),
1320            GPIOG: GPIOG::steal(),
1321            GPIOH: GPIOH::steal(),
1322            SAI1: SAI1::steal(),
1323            TIM2: TIM2::steal(),
1324            TIM3: TIM3::steal(),
1325            TIM4: TIM4::steal(),
1326            TIM5: TIM5::steal(),
1327            TIM15: TIM15::steal(),
1328            TIM16: TIM16::steal(),
1329            TIM17: TIM17::steal(),
1330            TIM1: TIM1::steal(),
1331            TIM8: TIM8::steal(),
1332            TIM6: TIM6::steal(),
1333            TIM7: TIM7::steal(),
1334            LPTIM1: LPTIM1::steal(),
1335            LPTIM2: LPTIM2::steal(),
1336            USART1: USART1::steal(),
1337            USART2: USART2::steal(),
1338            UART4: UART4::steal(),
1339            USART3: USART3::steal(),
1340            LPUART1: LPUART1::steal(),
1341            SPI1: SPI1::steal(),
1342            SPI3: SPI3::steal(),
1343            SPI2: SPI2::steal(),
1344            SDMMC: SDMMC::steal(),
1345            EXTI: EXTI::steal(),
1346            VREFBUF: VREFBUF::steal(),
1347            CAN1: CAN1::steal(),
1348            RTC: RTC::steal(),
1349            SWPMI1: SWPMI1::steal(),
1350            OPAMP: OPAMP::steal(),
1351            CRS: CRS::steal(),
1352            USB_SRAM: USB_SRAM::steal(),
1353            USB_FS: USB_FS::steal(),
1354            DFSDM: DFSDM::steal(),
1355            QUADSPI: QUADSPI::steal(),
1356            DBGMCU: DBGMCU::steal(),
1357        }
1358    }
1359}
stm32l4/stm32l4x1/mod.rs

stm32l4/stm32l4x1/
mod.rs
