stm32l4/stm32l4x1/flash/
acr.rs

1///Register `ACR` reader
2pub type R = crate::R<ACRrs>;
3///Register `ACR` writer
4pub type W = crate::W<ACRrs>;
5///Field `LATENCY` reader - Latency
6pub type LATENCY_R = crate::FieldReader;
7///Field `LATENCY` writer - Latency
8pub type LATENCY_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9///Field `PRFTEN` reader - Prefetch enable
10pub type PRFTEN_R = crate::BitReader;
11///Field `PRFTEN` writer - Prefetch enable
12pub type PRFTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `ICEN` reader - Instruction cache enable
14pub type ICEN_R = crate::BitReader;
15///Field `ICEN` writer - Instruction cache enable
16pub type ICEN_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `DCEN` reader - Data cache enable
18pub type DCEN_R = crate::BitReader;
19///Field `DCEN` writer - Data cache enable
20pub type DCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `ICRST` reader - Instruction cache reset
22pub type ICRST_R = crate::BitReader;
23///Field `ICRST` writer - Instruction cache reset
24pub type ICRST_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `DCRST` reader - Data cache reset
26pub type DCRST_R = crate::BitReader;
27///Field `DCRST` writer - Data cache reset
28pub type DCRST_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `RUN_PD` reader - Flash Power-down mode during Low-power run mode
30pub type RUN_PD_R = crate::BitReader;
31///Field `RUN_PD` writer - Flash Power-down mode during Low-power run mode
32pub type RUN_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `SLEEP_PD` reader - Flash Power-down mode during Low-power sleep mode
34pub type SLEEP_PD_R = crate::BitReader;
35///Field `SLEEP_PD` writer - Flash Power-down mode during Low-power sleep mode
36pub type SLEEP_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38    ///Bits 0:2 - Latency
39    #[inline(always)]
40    pub fn latency(&self) -> LATENCY_R {
41        LATENCY_R::new((self.bits & 7) as u8)
42    }
43    ///Bit 8 - Prefetch enable
44    #[inline(always)]
45    pub fn prften(&self) -> PRFTEN_R {
46        PRFTEN_R::new(((self.bits >> 8) & 1) != 0)
47    }
48    ///Bit 9 - Instruction cache enable
49    #[inline(always)]
50    pub fn icen(&self) -> ICEN_R {
51        ICEN_R::new(((self.bits >> 9) & 1) != 0)
52    }
53    ///Bit 10 - Data cache enable
54    #[inline(always)]
55    pub fn dcen(&self) -> DCEN_R {
56        DCEN_R::new(((self.bits >> 10) & 1) != 0)
57    }
58    ///Bit 11 - Instruction cache reset
59    #[inline(always)]
60    pub fn icrst(&self) -> ICRST_R {
61        ICRST_R::new(((self.bits >> 11) & 1) != 0)
62    }
63    ///Bit 12 - Data cache reset
64    #[inline(always)]
65    pub fn dcrst(&self) -> DCRST_R {
66        DCRST_R::new(((self.bits >> 12) & 1) != 0)
67    }
68    ///Bit 13 - Flash Power-down mode during Low-power run mode
69    #[inline(always)]
70    pub fn run_pd(&self) -> RUN_PD_R {
71        RUN_PD_R::new(((self.bits >> 13) & 1) != 0)
72    }
73    ///Bit 14 - Flash Power-down mode during Low-power sleep mode
74    #[inline(always)]
75    pub fn sleep_pd(&self) -> SLEEP_PD_R {
76        SLEEP_PD_R::new(((self.bits >> 14) & 1) != 0)
77    }
78}
79impl core::fmt::Debug for R {
80    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
81        f.debug_struct("ACR")
82            .field("latency", &self.latency())
83            .field("prften", &self.prften())
84            .field("icen", &self.icen())
85            .field("dcen", &self.dcen())
86            .field("icrst", &self.icrst())
87            .field("dcrst", &self.dcrst())
88            .field("run_pd", &self.run_pd())
89            .field("sleep_pd", &self.sleep_pd())
90            .finish()
91    }
92}
93impl W {
94    ///Bits 0:2 - Latency
95    #[inline(always)]
96    pub fn latency(&mut self) -> LATENCY_W<ACRrs> {
97        LATENCY_W::new(self, 0)
98    }
99    ///Bit 8 - Prefetch enable
100    #[inline(always)]
101    pub fn prften(&mut self) -> PRFTEN_W<ACRrs> {
102        PRFTEN_W::new(self, 8)
103    }
104    ///Bit 9 - Instruction cache enable
105    #[inline(always)]
106    pub fn icen(&mut self) -> ICEN_W<ACRrs> {
107        ICEN_W::new(self, 9)
108    }
109    ///Bit 10 - Data cache enable
110    #[inline(always)]
111    pub fn dcen(&mut self) -> DCEN_W<ACRrs> {
112        DCEN_W::new(self, 10)
113    }
114    ///Bit 11 - Instruction cache reset
115    #[inline(always)]
116    pub fn icrst(&mut self) -> ICRST_W<ACRrs> {
117        ICRST_W::new(self, 11)
118    }
119    ///Bit 12 - Data cache reset
120    #[inline(always)]
121    pub fn dcrst(&mut self) -> DCRST_W<ACRrs> {
122        DCRST_W::new(self, 12)
123    }
124    ///Bit 13 - Flash Power-down mode during Low-power run mode
125    #[inline(always)]
126    pub fn run_pd(&mut self) -> RUN_PD_W<ACRrs> {
127        RUN_PD_W::new(self, 13)
128    }
129    ///Bit 14 - Flash Power-down mode during Low-power sleep mode
130    #[inline(always)]
131    pub fn sleep_pd(&mut self) -> SLEEP_PD_W<ACRrs> {
132        SLEEP_PD_W::new(self, 14)
133    }
134}
135/**Access control register
136
137You can [`read`](crate::Reg::read) this register and get [`acr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
138
139See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#FLASH:ACR)*/
140pub struct ACRrs;
141impl crate::RegisterSpec for ACRrs {
142    type Ux = u32;
143}
144///`read()` method returns [`acr::R`](R) reader structure
145impl crate::Readable for ACRrs {}
146///`write(|w| ..)` method takes [`acr::W`](W) writer structure
147impl crate::Writable for ACRrs {
148    type Safety = crate::Unsafe;
149}
150///`reset()` method sets ACR to value 0x0600
151impl crate::Resettable for ACRrs {
152    const RESET_VALUE: u32 = 0x0600;
153}
stm32l4/stm32l4x1/flash/acr.rs

stm32l4/stm32l4x1/flash/
acr.rs
