stm32l4/stm32l4x1/dfsdm/flt/
cr1.rs

1///Register `CR1` reader
2pub type R = crate::R<CR1rs>;
3///Register `CR1` writer
4pub type W = crate::W<CR1rs>;
5/**DFSDM enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum DFEN {
11    ///0: DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped
12    Disabled = 0,
13    ///1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting
14    Enabled = 1,
15}
16impl From<DFEN> for bool {
17    #[inline(always)]
18    fn from(variant: DFEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `DFEN` reader - DFSDM enable
23pub type DFEN_R = crate::BitReader<DFEN>;
24impl DFEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> DFEN {
28        match self.bits {
29            false => DFEN::Disabled,
30            true => DFEN::Enabled,
31        }
32    }
33    ///DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == DFEN::Disabled
37    }
38    ///DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == DFEN::Enabled
42    }
43}
44///Field `DFEN` writer - DFSDM enable
45pub type DFEN_W<'a, REG> = crate::BitWriter<'a, REG, DFEN>;
46impl<'a, REG> DFEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(DFEN::Disabled)
54    }
55    ///DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(DFEN::Enabled)
59    }
60}
61/**Start a conversion of the injected group of channels
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum JSWSTARTW {
67    ///1: Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing ‘1’ has no effect if JSYNC=1
68    Start = 1,
69}
70impl From<JSWSTARTW> for bool {
71    #[inline(always)]
72    fn from(variant: JSWSTARTW) -> Self {
73        variant as u8 != 0
74    }
75}
76///Field `JSWSTART` reader - Start a conversion of the injected group of channels
77pub type JSWSTART_R = crate::BitReader<JSWSTARTW>;
78impl JSWSTART_R {
79    ///Get enumerated values variant
80    #[inline(always)]
81    pub const fn variant(&self) -> Option<JSWSTARTW> {
82        match self.bits {
83            true => Some(JSWSTARTW::Start),
84            _ => None,
85        }
86    }
87    ///Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing ‘1’ has no effect if JSYNC=1
88    #[inline(always)]
89    pub fn is_start(&self) -> bool {
90        *self == JSWSTARTW::Start
91    }
92}
93///Field `JSWSTART` writer - Start a conversion of the injected group of channels
94pub type JSWSTART_W<'a, REG> = crate::BitWriter<'a, REG, JSWSTARTW>;
95impl<'a, REG> JSWSTART_W<'a, REG>
96where
97    REG: crate::Writable + crate::RegisterSpec,
98{
99    ///Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing ‘1’ has no effect if JSYNC=1
100    #[inline(always)]
101    pub fn start(self) -> &'a mut crate::W<REG> {
102        self.variant(JSWSTARTW::Start)
103    }
104}
105/**Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
106
107Value on reset: 0*/
108#[cfg_attr(feature = "defmt", derive(defmt::Format))]
109#[derive(Clone, Copy, Debug, PartialEq, Eq)]
110pub enum JSYNC {
111    ///0: Do not launch an injected conversion synchronously with DFSDM_FLT0
112    Disabled = 0,
113    ///1: Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
114    Enabled = 1,
115}
116impl From<JSYNC> for bool {
117    #[inline(always)]
118    fn from(variant: JSYNC) -> Self {
119        variant as u8 != 0
120    }
121}
122///Field `JSYNC` reader - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
123pub type JSYNC_R = crate::BitReader<JSYNC>;
124impl JSYNC_R {
125    ///Get enumerated values variant
126    #[inline(always)]
127    pub const fn variant(&self) -> JSYNC {
128        match self.bits {
129            false => JSYNC::Disabled,
130            true => JSYNC::Enabled,
131        }
132    }
133    ///Do not launch an injected conversion synchronously with DFSDM_FLT0
134    #[inline(always)]
135    pub fn is_disabled(&self) -> bool {
136        *self == JSYNC::Disabled
137    }
138    ///Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
139    #[inline(always)]
140    pub fn is_enabled(&self) -> bool {
141        *self == JSYNC::Enabled
142    }
143}
144///Field `JSYNC` writer - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
145pub type JSYNC_W<'a, REG> = crate::BitWriter<'a, REG, JSYNC>;
146impl<'a, REG> JSYNC_W<'a, REG>
147where
148    REG: crate::Writable + crate::RegisterSpec,
149{
150    ///Do not launch an injected conversion synchronously with DFSDM_FLT0
151    #[inline(always)]
152    pub fn disabled(self) -> &'a mut crate::W<REG> {
153        self.variant(JSYNC::Disabled)
154    }
155    ///Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
156    #[inline(always)]
157    pub fn enabled(self) -> &'a mut crate::W<REG> {
158        self.variant(JSYNC::Enabled)
159    }
160}
161/**Scanning conversion mode for injected conversions
162
163Value on reset: 0*/
164#[cfg_attr(feature = "defmt", derive(defmt::Format))]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum JSCAN {
167    ///0: One channel conversion is performed from the injected channel group and next the selected channel from this group is selected
168    Single = 0,
169    ///1: The series of conversions for the injected group channels is executed, starting over with the lowest selected channel
170    Series = 1,
171}
172impl From<JSCAN> for bool {
173    #[inline(always)]
174    fn from(variant: JSCAN) -> Self {
175        variant as u8 != 0
176    }
177}
178///Field `JSCAN` reader - Scanning conversion mode for injected conversions
179pub type JSCAN_R = crate::BitReader<JSCAN>;
180impl JSCAN_R {
181    ///Get enumerated values variant
182    #[inline(always)]
183    pub const fn variant(&self) -> JSCAN {
184        match self.bits {
185            false => JSCAN::Single,
186            true => JSCAN::Series,
187        }
188    }
189    ///One channel conversion is performed from the injected channel group and next the selected channel from this group is selected
190    #[inline(always)]
191    pub fn is_single(&self) -> bool {
192        *self == JSCAN::Single
193    }
194    ///The series of conversions for the injected group channels is executed, starting over with the lowest selected channel
195    #[inline(always)]
196    pub fn is_series(&self) -> bool {
197        *self == JSCAN::Series
198    }
199}
200///Field `JSCAN` writer - Scanning conversion mode for injected conversions
201pub type JSCAN_W<'a, REG> = crate::BitWriter<'a, REG, JSCAN>;
202impl<'a, REG> JSCAN_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    ///One channel conversion is performed from the injected channel group and next the selected channel from this group is selected
207    #[inline(always)]
208    pub fn single(self) -> &'a mut crate::W<REG> {
209        self.variant(JSCAN::Single)
210    }
211    ///The series of conversions for the injected group channels is executed, starting over with the lowest selected channel
212    #[inline(always)]
213    pub fn series(self) -> &'a mut crate::W<REG> {
214        self.variant(JSCAN::Series)
215    }
216}
217/**DMA channel enabled to read data for the injected channel group
218
219Value on reset: 0*/
220#[cfg_attr(feature = "defmt", derive(defmt::Format))]
221#[derive(Clone, Copy, Debug, PartialEq, Eq)]
222pub enum JDMAEN {
223    ///0: The DMA channel is not enabled to read injected data
224    Disabled = 0,
225    ///1: The DMA channel is enabled to read injected data
226    Enabled = 1,
227}
228impl From<JDMAEN> for bool {
229    #[inline(always)]
230    fn from(variant: JDMAEN) -> Self {
231        variant as u8 != 0
232    }
233}
234///Field `JDMAEN` reader - DMA channel enabled to read data for the injected channel group
235pub type JDMAEN_R = crate::BitReader<JDMAEN>;
236impl JDMAEN_R {
237    ///Get enumerated values variant
238    #[inline(always)]
239    pub const fn variant(&self) -> JDMAEN {
240        match self.bits {
241            false => JDMAEN::Disabled,
242            true => JDMAEN::Enabled,
243        }
244    }
245    ///The DMA channel is not enabled to read injected data
246    #[inline(always)]
247    pub fn is_disabled(&self) -> bool {
248        *self == JDMAEN::Disabled
249    }
250    ///The DMA channel is enabled to read injected data
251    #[inline(always)]
252    pub fn is_enabled(&self) -> bool {
253        *self == JDMAEN::Enabled
254    }
255}
256///Field `JDMAEN` writer - DMA channel enabled to read data for the injected channel group
257pub type JDMAEN_W<'a, REG> = crate::BitWriter<'a, REG, JDMAEN>;
258impl<'a, REG> JDMAEN_W<'a, REG>
259where
260    REG: crate::Writable + crate::RegisterSpec,
261{
262    ///The DMA channel is not enabled to read injected data
263    #[inline(always)]
264    pub fn disabled(self) -> &'a mut crate::W<REG> {
265        self.variant(JDMAEN::Disabled)
266    }
267    ///The DMA channel is enabled to read injected data
268    #[inline(always)]
269    pub fn enabled(self) -> &'a mut crate::W<REG> {
270        self.variant(JDMAEN::Enabled)
271    }
272}
273///Field `JEXTSEL` reader - Trigger signal selection for launching injected conversions
274pub type JEXTSEL_R = crate::FieldReader;
275///Field `JEXTSEL` writer - Trigger signal selection for launching injected conversions
276pub type JEXTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
277/**Trigger enable and trigger edge selection for injected conversions
278
279Value on reset: 0*/
280#[cfg_attr(feature = "defmt", derive(defmt::Format))]
281#[derive(Clone, Copy, Debug, PartialEq, Eq)]
282#[repr(u8)]
283pub enum JEXTEN {
284    ///0: Trigger detection is disabled
285    Disabled = 0,
286    ///1: Each rising edge on the selected trigger makes a request to launch an injected conversion
287    RisingEdge = 1,
288    ///2: Each falling edge on the selected trigger makes a request to launch an injected conversion
289    FallingEdge = 2,
290    ///3: Both rising edges and falling edges on the selected trigger make requests to launch injected conversions
291    BothEdges = 3,
292}
293impl From<JEXTEN> for u8 {
294    #[inline(always)]
295    fn from(variant: JEXTEN) -> Self {
296        variant as _
297    }
298}
299impl crate::FieldSpec for JEXTEN {
300    type Ux = u8;
301}
302impl crate::IsEnum for JEXTEN {}
303///Field `JEXTEN` reader - Trigger enable and trigger edge selection for injected conversions
304pub type JEXTEN_R = crate::FieldReader<JEXTEN>;
305impl JEXTEN_R {
306    ///Get enumerated values variant
307    #[inline(always)]
308    pub const fn variant(&self) -> JEXTEN {
309        match self.bits {
310            0 => JEXTEN::Disabled,
311            1 => JEXTEN::RisingEdge,
312            2 => JEXTEN::FallingEdge,
313            3 => JEXTEN::BothEdges,
314            _ => unreachable!(),
315        }
316    }
317    ///Trigger detection is disabled
318    #[inline(always)]
319    pub fn is_disabled(&self) -> bool {
320        *self == JEXTEN::Disabled
321    }
322    ///Each rising edge on the selected trigger makes a request to launch an injected conversion
323    #[inline(always)]
324    pub fn is_rising_edge(&self) -> bool {
325        *self == JEXTEN::RisingEdge
326    }
327    ///Each falling edge on the selected trigger makes a request to launch an injected conversion
328    #[inline(always)]
329    pub fn is_falling_edge(&self) -> bool {
330        *self == JEXTEN::FallingEdge
331    }
332    ///Both rising edges and falling edges on the selected trigger make requests to launch injected conversions
333    #[inline(always)]
334    pub fn is_both_edges(&self) -> bool {
335        *self == JEXTEN::BothEdges
336    }
337}
338///Field `JEXTEN` writer - Trigger enable and trigger edge selection for injected conversions
339pub type JEXTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, JEXTEN, crate::Safe>;
340impl<'a, REG> JEXTEN_W<'a, REG>
341where
342    REG: crate::Writable + crate::RegisterSpec,
343    REG::Ux: From<u8>,
344{
345    ///Trigger detection is disabled
346    #[inline(always)]
347    pub fn disabled(self) -> &'a mut crate::W<REG> {
348        self.variant(JEXTEN::Disabled)
349    }
350    ///Each rising edge on the selected trigger makes a request to launch an injected conversion
351    #[inline(always)]
352    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
353        self.variant(JEXTEN::RisingEdge)
354    }
355    ///Each falling edge on the selected trigger makes a request to launch an injected conversion
356    #[inline(always)]
357    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
358        self.variant(JEXTEN::FallingEdge)
359    }
360    ///Both rising edges and falling edges on the selected trigger make requests to launch injected conversions
361    #[inline(always)]
362    pub fn both_edges(self) -> &'a mut crate::W<REG> {
363        self.variant(JEXTEN::BothEdges)
364    }
365}
366/**Software start of a conversion on the regular channel
367
368Value on reset: 0*/
369#[cfg_attr(feature = "defmt", derive(defmt::Format))]
370#[derive(Clone, Copy, Debug, PartialEq, Eq)]
371pub enum RSWSTARTW {
372    ///1: Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if RSYNC=1
373    Start = 1,
374}
375impl From<RSWSTARTW> for bool {
376    #[inline(always)]
377    fn from(variant: RSWSTARTW) -> Self {
378        variant as u8 != 0
379    }
380}
381///Field `RSWSTART` reader - Software start of a conversion on the regular channel
382pub type RSWSTART_R = crate::BitReader<RSWSTARTW>;
383impl RSWSTART_R {
384    ///Get enumerated values variant
385    #[inline(always)]
386    pub const fn variant(&self) -> Option<RSWSTARTW> {
387        match self.bits {
388            true => Some(RSWSTARTW::Start),
389            _ => None,
390        }
391    }
392    ///Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if RSYNC=1
393    #[inline(always)]
394    pub fn is_start(&self) -> bool {
395        *self == RSWSTARTW::Start
396    }
397}
398///Field `RSWSTART` writer - Software start of a conversion on the regular channel
399pub type RSWSTART_W<'a, REG> = crate::BitWriter<'a, REG, RSWSTARTW>;
400impl<'a, REG> RSWSTART_W<'a, REG>
401where
402    REG: crate::Writable + crate::RegisterSpec,
403{
404    ///Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if RSYNC=1
405    #[inline(always)]
406    pub fn start(self) -> &'a mut crate::W<REG> {
407        self.variant(RSWSTARTW::Start)
408    }
409}
410/**Continuous mode selection for regular conversions
411
412Value on reset: 0*/
413#[cfg_attr(feature = "defmt", derive(defmt::Format))]
414#[derive(Clone, Copy, Debug, PartialEq, Eq)]
415pub enum RCONT {
416    ///0: The regular channel is converted just once for each conversion request
417    Once = 0,
418    ///1: The regular channel is converted repeatedly after each conversion request
419    Continuous = 1,
420}
421impl From<RCONT> for bool {
422    #[inline(always)]
423    fn from(variant: RCONT) -> Self {
424        variant as u8 != 0
425    }
426}
427///Field `RCONT` reader - Continuous mode selection for regular conversions
428pub type RCONT_R = crate::BitReader<RCONT>;
429impl RCONT_R {
430    ///Get enumerated values variant
431    #[inline(always)]
432    pub const fn variant(&self) -> RCONT {
433        match self.bits {
434            false => RCONT::Once,
435            true => RCONT::Continuous,
436        }
437    }
438    ///The regular channel is converted just once for each conversion request
439    #[inline(always)]
440    pub fn is_once(&self) -> bool {
441        *self == RCONT::Once
442    }
443    ///The regular channel is converted repeatedly after each conversion request
444    #[inline(always)]
445    pub fn is_continuous(&self) -> bool {
446        *self == RCONT::Continuous
447    }
448}
449///Field `RCONT` writer - Continuous mode selection for regular conversions
450pub type RCONT_W<'a, REG> = crate::BitWriter<'a, REG, RCONT>;
451impl<'a, REG> RCONT_W<'a, REG>
452where
453    REG: crate::Writable + crate::RegisterSpec,
454{
455    ///The regular channel is converted just once for each conversion request
456    #[inline(always)]
457    pub fn once(self) -> &'a mut crate::W<REG> {
458        self.variant(RCONT::Once)
459    }
460    ///The regular channel is converted repeatedly after each conversion request
461    #[inline(always)]
462    pub fn continuous(self) -> &'a mut crate::W<REG> {
463        self.variant(RCONT::Continuous)
464    }
465}
466/**Launch regular conversion synchronously with DFSDM0
467
468Value on reset: 0*/
469#[cfg_attr(feature = "defmt", derive(defmt::Format))]
470#[derive(Clone, Copy, Debug, PartialEq, Eq)]
471pub enum RSYNC {
472    ///0: Do not launch a regular conversion synchronously with DFSDM_FLT0
473    NoLaunch = 0,
474    ///1: Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0
475    Launch = 1,
476}
477impl From<RSYNC> for bool {
478    #[inline(always)]
479    fn from(variant: RSYNC) -> Self {
480        variant as u8 != 0
481    }
482}
483///Field `RSYNC` reader - Launch regular conversion synchronously with DFSDM0
484pub type RSYNC_R = crate::BitReader<RSYNC>;
485impl RSYNC_R {
486    ///Get enumerated values variant
487    #[inline(always)]
488    pub const fn variant(&self) -> RSYNC {
489        match self.bits {
490            false => RSYNC::NoLaunch,
491            true => RSYNC::Launch,
492        }
493    }
494    ///Do not launch a regular conversion synchronously with DFSDM_FLT0
495    #[inline(always)]
496    pub fn is_no_launch(&self) -> bool {
497        *self == RSYNC::NoLaunch
498    }
499    ///Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0
500    #[inline(always)]
501    pub fn is_launch(&self) -> bool {
502        *self == RSYNC::Launch
503    }
504}
505///Field `RSYNC` writer - Launch regular conversion synchronously with DFSDM0
506pub type RSYNC_W<'a, REG> = crate::BitWriter<'a, REG, RSYNC>;
507impl<'a, REG> RSYNC_W<'a, REG>
508where
509    REG: crate::Writable + crate::RegisterSpec,
510{
511    ///Do not launch a regular conversion synchronously with DFSDM_FLT0
512    #[inline(always)]
513    pub fn no_launch(self) -> &'a mut crate::W<REG> {
514        self.variant(RSYNC::NoLaunch)
515    }
516    ///Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0
517    #[inline(always)]
518    pub fn launch(self) -> &'a mut crate::W<REG> {
519        self.variant(RSYNC::Launch)
520    }
521}
522/**DMA channel enabled to read data for the regular conversion
523
524Value on reset: 0*/
525#[cfg_attr(feature = "defmt", derive(defmt::Format))]
526#[derive(Clone, Copy, Debug, PartialEq, Eq)]
527pub enum RDMAEN {
528    ///0: The DMA channel is not enabled to read regular data
529    Disabled = 0,
530    ///1: The DMA channel is enabled to read regular data
531    Enabled = 1,
532}
533impl From<RDMAEN> for bool {
534    #[inline(always)]
535    fn from(variant: RDMAEN) -> Self {
536        variant as u8 != 0
537    }
538}
539///Field `RDMAEN` reader - DMA channel enabled to read data for the regular conversion
540pub type RDMAEN_R = crate::BitReader<RDMAEN>;
541impl RDMAEN_R {
542    ///Get enumerated values variant
543    #[inline(always)]
544    pub const fn variant(&self) -> RDMAEN {
545        match self.bits {
546            false => RDMAEN::Disabled,
547            true => RDMAEN::Enabled,
548        }
549    }
550    ///The DMA channel is not enabled to read regular data
551    #[inline(always)]
552    pub fn is_disabled(&self) -> bool {
553        *self == RDMAEN::Disabled
554    }
555    ///The DMA channel is enabled to read regular data
556    #[inline(always)]
557    pub fn is_enabled(&self) -> bool {
558        *self == RDMAEN::Enabled
559    }
560}
561///Field `RDMAEN` writer - DMA channel enabled to read data for the regular conversion
562pub type RDMAEN_W<'a, REG> = crate::BitWriter<'a, REG, RDMAEN>;
563impl<'a, REG> RDMAEN_W<'a, REG>
564where
565    REG: crate::Writable + crate::RegisterSpec,
566{
567    ///The DMA channel is not enabled to read regular data
568    #[inline(always)]
569    pub fn disabled(self) -> &'a mut crate::W<REG> {
570        self.variant(RDMAEN::Disabled)
571    }
572    ///The DMA channel is enabled to read regular data
573    #[inline(always)]
574    pub fn enabled(self) -> &'a mut crate::W<REG> {
575        self.variant(RDMAEN::Enabled)
576    }
577}
578/**Regular channel selection
579
580Value on reset: 0*/
581#[cfg_attr(feature = "defmt", derive(defmt::Format))]
582#[derive(Clone, Copy, Debug, PartialEq, Eq)]
583#[repr(u8)]
584pub enum RCH {
585    ///0: Channel 0 is selected as regular channel
586    Channel0 = 0,
587    ///1: Channel 1 is selected as regular channel
588    Channel1 = 1,
589    ///2: Channel 2 is selected as regular channel
590    Channel2 = 2,
591    ///3: Channel 3 is selected as regular channel
592    Channel3 = 3,
593    ///4: Channel 4 is selected as regular channel
594    Channel4 = 4,
595    ///5: Channel 5 is selected as regular channel
596    Channel5 = 5,
597    ///6: Channel 6 is selected as regular channel
598    Channel6 = 6,
599    ///7: Channel 7 is selected as regular channel
600    Channel7 = 7,
601}
602impl From<RCH> for u8 {
603    #[inline(always)]
604    fn from(variant: RCH) -> Self {
605        variant as _
606    }
607}
608impl crate::FieldSpec for RCH {
609    type Ux = u8;
610}
611impl crate::IsEnum for RCH {}
612///Field `RCH` reader - Regular channel selection
613pub type RCH_R = crate::FieldReader<RCH>;
614impl RCH_R {
615    ///Get enumerated values variant
616    #[inline(always)]
617    pub const fn variant(&self) -> RCH {
618        match self.bits {
619            0 => RCH::Channel0,
620            1 => RCH::Channel1,
621            2 => RCH::Channel2,
622            3 => RCH::Channel3,
623            4 => RCH::Channel4,
624            5 => RCH::Channel5,
625            6 => RCH::Channel6,
626            7 => RCH::Channel7,
627            _ => unreachable!(),
628        }
629    }
630    ///Channel 0 is selected as regular channel
631    #[inline(always)]
632    pub fn is_channel0(&self) -> bool {
633        *self == RCH::Channel0
634    }
635    ///Channel 1 is selected as regular channel
636    #[inline(always)]
637    pub fn is_channel1(&self) -> bool {
638        *self == RCH::Channel1
639    }
640    ///Channel 2 is selected as regular channel
641    #[inline(always)]
642    pub fn is_channel2(&self) -> bool {
643        *self == RCH::Channel2
644    }
645    ///Channel 3 is selected as regular channel
646    #[inline(always)]
647    pub fn is_channel3(&self) -> bool {
648        *self == RCH::Channel3
649    }
650    ///Channel 4 is selected as regular channel
651    #[inline(always)]
652    pub fn is_channel4(&self) -> bool {
653        *self == RCH::Channel4
654    }
655    ///Channel 5 is selected as regular channel
656    #[inline(always)]
657    pub fn is_channel5(&self) -> bool {
658        *self == RCH::Channel5
659    }
660    ///Channel 6 is selected as regular channel
661    #[inline(always)]
662    pub fn is_channel6(&self) -> bool {
663        *self == RCH::Channel6
664    }
665    ///Channel 7 is selected as regular channel
666    #[inline(always)]
667    pub fn is_channel7(&self) -> bool {
668        *self == RCH::Channel7
669    }
670}
671///Field `RCH` writer - Regular channel selection
672pub type RCH_W<'a, REG> = crate::FieldWriter<'a, REG, 3, RCH, crate::Safe>;
673impl<'a, REG> RCH_W<'a, REG>
674where
675    REG: crate::Writable + crate::RegisterSpec,
676    REG::Ux: From<u8>,
677{
678    ///Channel 0 is selected as regular channel
679    #[inline(always)]
680    pub fn channel0(self) -> &'a mut crate::W<REG> {
681        self.variant(RCH::Channel0)
682    }
683    ///Channel 1 is selected as regular channel
684    #[inline(always)]
685    pub fn channel1(self) -> &'a mut crate::W<REG> {
686        self.variant(RCH::Channel1)
687    }
688    ///Channel 2 is selected as regular channel
689    #[inline(always)]
690    pub fn channel2(self) -> &'a mut crate::W<REG> {
691        self.variant(RCH::Channel2)
692    }
693    ///Channel 3 is selected as regular channel
694    #[inline(always)]
695    pub fn channel3(self) -> &'a mut crate::W<REG> {
696        self.variant(RCH::Channel3)
697    }
698    ///Channel 4 is selected as regular channel
699    #[inline(always)]
700    pub fn channel4(self) -> &'a mut crate::W<REG> {
701        self.variant(RCH::Channel4)
702    }
703    ///Channel 5 is selected as regular channel
704    #[inline(always)]
705    pub fn channel5(self) -> &'a mut crate::W<REG> {
706        self.variant(RCH::Channel5)
707    }
708    ///Channel 6 is selected as regular channel
709    #[inline(always)]
710    pub fn channel6(self) -> &'a mut crate::W<REG> {
711        self.variant(RCH::Channel6)
712    }
713    ///Channel 7 is selected as regular channel
714    #[inline(always)]
715    pub fn channel7(self) -> &'a mut crate::W<REG> {
716        self.variant(RCH::Channel7)
717    }
718}
719/**Fast conversion mode selection for regular conversions
720
721Value on reset: 0*/
722#[cfg_attr(feature = "defmt", derive(defmt::Format))]
723#[derive(Clone, Copy, Debug, PartialEq, Eq)]
724pub enum FAST {
725    ///0: Fast conversion mode disabled
726    Disabled = 0,
727    ///1: Fast conversion mode enabled
728    Enabled = 1,
729}
730impl From<FAST> for bool {
731    #[inline(always)]
732    fn from(variant: FAST) -> Self {
733        variant as u8 != 0
734    }
735}
736///Field `FAST` reader - Fast conversion mode selection for regular conversions
737pub type FAST_R = crate::BitReader<FAST>;
738impl FAST_R {
739    ///Get enumerated values variant
740    #[inline(always)]
741    pub const fn variant(&self) -> FAST {
742        match self.bits {
743            false => FAST::Disabled,
744            true => FAST::Enabled,
745        }
746    }
747    ///Fast conversion mode disabled
748    #[inline(always)]
749    pub fn is_disabled(&self) -> bool {
750        *self == FAST::Disabled
751    }
752    ///Fast conversion mode enabled
753    #[inline(always)]
754    pub fn is_enabled(&self) -> bool {
755        *self == FAST::Enabled
756    }
757}
758///Field `FAST` writer - Fast conversion mode selection for regular conversions
759pub type FAST_W<'a, REG> = crate::BitWriter<'a, REG, FAST>;
760impl<'a, REG> FAST_W<'a, REG>
761where
762    REG: crate::Writable + crate::RegisterSpec,
763{
764    ///Fast conversion mode disabled
765    #[inline(always)]
766    pub fn disabled(self) -> &'a mut crate::W<REG> {
767        self.variant(FAST::Disabled)
768    }
769    ///Fast conversion mode enabled
770    #[inline(always)]
771    pub fn enabled(self) -> &'a mut crate::W<REG> {
772        self.variant(FAST::Enabled)
773    }
774}
775/**Analog watchdog fast mode select
776
777Value on reset: 0*/
778#[cfg_attr(feature = "defmt", derive(defmt::Format))]
779#[derive(Clone, Copy, Debug, PartialEq, Eq)]
780pub enum AWFSEL {
781    ///0: Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
782    Output = 0,
783    ///1: Analog watchdog on channel transceivers value (after watchdog filter)
784    Transceiver = 1,
785}
786impl From<AWFSEL> for bool {
787    #[inline(always)]
788    fn from(variant: AWFSEL) -> Self {
789        variant as u8 != 0
790    }
791}
792///Field `AWFSEL` reader - Analog watchdog fast mode select
793pub type AWFSEL_R = crate::BitReader<AWFSEL>;
794impl AWFSEL_R {
795    ///Get enumerated values variant
796    #[inline(always)]
797    pub const fn variant(&self) -> AWFSEL {
798        match self.bits {
799            false => AWFSEL::Output,
800            true => AWFSEL::Transceiver,
801        }
802    }
803    ///Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
804    #[inline(always)]
805    pub fn is_output(&self) -> bool {
806        *self == AWFSEL::Output
807    }
808    ///Analog watchdog on channel transceivers value (after watchdog filter)
809    #[inline(always)]
810    pub fn is_transceiver(&self) -> bool {
811        *self == AWFSEL::Transceiver
812    }
813}
814///Field `AWFSEL` writer - Analog watchdog fast mode select
815pub type AWFSEL_W<'a, REG> = crate::BitWriter<'a, REG, AWFSEL>;
816impl<'a, REG> AWFSEL_W<'a, REG>
817where
818    REG: crate::Writable + crate::RegisterSpec,
819{
820    ///Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
821    #[inline(always)]
822    pub fn output(self) -> &'a mut crate::W<REG> {
823        self.variant(AWFSEL::Output)
824    }
825    ///Analog watchdog on channel transceivers value (after watchdog filter)
826    #[inline(always)]
827    pub fn transceiver(self) -> &'a mut crate::W<REG> {
828        self.variant(AWFSEL::Transceiver)
829    }
830}
831impl R {
832    ///Bit 0 - DFSDM enable
833    #[inline(always)]
834    pub fn dfen(&self) -> DFEN_R {
835        DFEN_R::new((self.bits & 1) != 0)
836    }
837    ///Bit 1 - Start a conversion of the injected group of channels
838    #[inline(always)]
839    pub fn jswstart(&self) -> JSWSTART_R {
840        JSWSTART_R::new(((self.bits >> 1) & 1) != 0)
841    }
842    ///Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
843    #[inline(always)]
844    pub fn jsync(&self) -> JSYNC_R {
845        JSYNC_R::new(((self.bits >> 3) & 1) != 0)
846    }
847    ///Bit 4 - Scanning conversion mode for injected conversions
848    #[inline(always)]
849    pub fn jscan(&self) -> JSCAN_R {
850        JSCAN_R::new(((self.bits >> 4) & 1) != 0)
851    }
852    ///Bit 5 - DMA channel enabled to read data for the injected channel group
853    #[inline(always)]
854    pub fn jdmaen(&self) -> JDMAEN_R {
855        JDMAEN_R::new(((self.bits >> 5) & 1) != 0)
856    }
857    ///Bits 8:10 - Trigger signal selection for launching injected conversions
858    #[inline(always)]
859    pub fn jextsel(&self) -> JEXTSEL_R {
860        JEXTSEL_R::new(((self.bits >> 8) & 7) as u8)
861    }
862    ///Bits 13:14 - Trigger enable and trigger edge selection for injected conversions
863    #[inline(always)]
864    pub fn jexten(&self) -> JEXTEN_R {
865        JEXTEN_R::new(((self.bits >> 13) & 3) as u8)
866    }
867    ///Bit 17 - Software start of a conversion on the regular channel
868    #[inline(always)]
869    pub fn rswstart(&self) -> RSWSTART_R {
870        RSWSTART_R::new(((self.bits >> 17) & 1) != 0)
871    }
872    ///Bit 18 - Continuous mode selection for regular conversions
873    #[inline(always)]
874    pub fn rcont(&self) -> RCONT_R {
875        RCONT_R::new(((self.bits >> 18) & 1) != 0)
876    }
877    ///Bit 19 - Launch regular conversion synchronously with DFSDM0
878    #[inline(always)]
879    pub fn rsync(&self) -> RSYNC_R {
880        RSYNC_R::new(((self.bits >> 19) & 1) != 0)
881    }
882    ///Bit 21 - DMA channel enabled to read data for the regular conversion
883    #[inline(always)]
884    pub fn rdmaen(&self) -> RDMAEN_R {
885        RDMAEN_R::new(((self.bits >> 21) & 1) != 0)
886    }
887    ///Bits 24:26 - Regular channel selection
888    #[inline(always)]
889    pub fn rch(&self) -> RCH_R {
890        RCH_R::new(((self.bits >> 24) & 7) as u8)
891    }
892    ///Bit 29 - Fast conversion mode selection for regular conversions
893    #[inline(always)]
894    pub fn fast(&self) -> FAST_R {
895        FAST_R::new(((self.bits >> 29) & 1) != 0)
896    }
897    ///Bit 30 - Analog watchdog fast mode select
898    #[inline(always)]
899    pub fn awfsel(&self) -> AWFSEL_R {
900        AWFSEL_R::new(((self.bits >> 30) & 1) != 0)
901    }
902}
903impl core::fmt::Debug for R {
904    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
905        f.debug_struct("CR1")
906            .field("awfsel", &self.awfsel())
907            .field("fast", &self.fast())
908            .field("rch", &self.rch())
909            .field("rdmaen", &self.rdmaen())
910            .field("rsync", &self.rsync())
911            .field("rcont", &self.rcont())
912            .field("rswstart", &self.rswstart())
913            .field("jexten", &self.jexten())
914            .field("jextsel", &self.jextsel())
915            .field("jdmaen", &self.jdmaen())
916            .field("jscan", &self.jscan())
917            .field("jsync", &self.jsync())
918            .field("jswstart", &self.jswstart())
919            .field("dfen", &self.dfen())
920            .finish()
921    }
922}
923impl W {
924    ///Bit 0 - DFSDM enable
925    #[inline(always)]
926    pub fn dfen(&mut self) -> DFEN_W<CR1rs> {
927        DFEN_W::new(self, 0)
928    }
929    ///Bit 1 - Start a conversion of the injected group of channels
930    #[inline(always)]
931    pub fn jswstart(&mut self) -> JSWSTART_W<CR1rs> {
932        JSWSTART_W::new(self, 1)
933    }
934    ///Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
935    #[inline(always)]
936    pub fn jsync(&mut self) -> JSYNC_W<CR1rs> {
937        JSYNC_W::new(self, 3)
938    }
939    ///Bit 4 - Scanning conversion mode for injected conversions
940    #[inline(always)]
941    pub fn jscan(&mut self) -> JSCAN_W<CR1rs> {
942        JSCAN_W::new(self, 4)
943    }
944    ///Bit 5 - DMA channel enabled to read data for the injected channel group
945    #[inline(always)]
946    pub fn jdmaen(&mut self) -> JDMAEN_W<CR1rs> {
947        JDMAEN_W::new(self, 5)
948    }
949    ///Bits 8:10 - Trigger signal selection for launching injected conversions
950    #[inline(always)]
951    pub fn jextsel(&mut self) -> JEXTSEL_W<CR1rs> {
952        JEXTSEL_W::new(self, 8)
953    }
954    ///Bits 13:14 - Trigger enable and trigger edge selection for injected conversions
955    #[inline(always)]
956    pub fn jexten(&mut self) -> JEXTEN_W<CR1rs> {
957        JEXTEN_W::new(self, 13)
958    }
959    ///Bit 17 - Software start of a conversion on the regular channel
960    #[inline(always)]
961    pub fn rswstart(&mut self) -> RSWSTART_W<CR1rs> {
962        RSWSTART_W::new(self, 17)
963    }
964    ///Bit 18 - Continuous mode selection for regular conversions
965    #[inline(always)]
966    pub fn rcont(&mut self) -> RCONT_W<CR1rs> {
967        RCONT_W::new(self, 18)
968    }
969    ///Bit 19 - Launch regular conversion synchronously with DFSDM0
970    #[inline(always)]
971    pub fn rsync(&mut self) -> RSYNC_W<CR1rs> {
972        RSYNC_W::new(self, 19)
973    }
974    ///Bit 21 - DMA channel enabled to read data for the regular conversion
975    #[inline(always)]
976    pub fn rdmaen(&mut self) -> RDMAEN_W<CR1rs> {
977        RDMAEN_W::new(self, 21)
978    }
979    ///Bits 24:26 - Regular channel selection
980    #[inline(always)]
981    pub fn rch(&mut self) -> RCH_W<CR1rs> {
982        RCH_W::new(self, 24)
983    }
984    ///Bit 29 - Fast conversion mode selection for regular conversions
985    #[inline(always)]
986    pub fn fast(&mut self) -> FAST_W<CR1rs> {
987        FAST_W::new(self, 29)
988    }
989    ///Bit 30 - Analog watchdog fast mode select
990    #[inline(always)]
991    pub fn awfsel(&mut self) -> AWFSEL_W<CR1rs> {
992        AWFSEL_W::new(self, 30)
993    }
994}
995/**control register 1
996
997You can [`read`](crate::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
998pub struct CR1rs;
999impl crate::RegisterSpec for CR1rs {
1000    type Ux = u32;
1001}
1002///`read()` method returns [`cr1::R`](R) reader structure
1003impl crate::Readable for CR1rs {}
1004///`write(|w| ..)` method takes [`cr1::W`](W) writer structure
1005impl crate::Writable for CR1rs {
1006    type Safety = crate::Unsafe;
1007}
1008///`reset()` method sets CR1 to value 0
1009impl crate::Resettable for CR1rs {}
stm32l4/stm32l4x1/dfsdm/flt/cr1.rs

stm32l4/stm32l4x1/dfsdm/flt/
cr1.rs
