stm32l4/stm32l4x1/comp/
comp1_csr.rs

1///Register `COMP1_CSR` reader
2pub type R = crate::R<COMP1_CSRrs>;
3///Register `COMP1_CSR` writer
4pub type W = crate::W<COMP1_CSRrs>;
5/**Comparator 1 enable bit
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum EN {
11    ///0: Comparator 1 disabled
12    Disabled = 0,
13    ///1: Comparator 1 enabled
14    Enabled = 1,
15}
16impl From<EN> for bool {
17    #[inline(always)]
18    fn from(variant: EN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `EN` reader - Comparator 1 enable bit
23pub type EN_R = crate::BitReader<EN>;
24impl EN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> EN {
28        match self.bits {
29            false => EN::Disabled,
30            true => EN::Enabled,
31        }
32    }
33    ///Comparator 1 disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == EN::Disabled
37    }
38    ///Comparator 1 enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == EN::Enabled
42    }
43}
44///Field `EN` writer - Comparator 1 enable bit
45pub type EN_W<'a, REG> = crate::BitWriter<'a, REG, EN>;
46impl<'a, REG> EN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Comparator 1 disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(EN::Disabled)
54    }
55    ///Comparator 1 enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(EN::Enabled)
59    }
60}
61/**Power Mode of the comparator 1
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66#[repr(u8)]
67pub enum PWRMODE {
68    ///0: High speed / full power
69    HighSpeed = 0,
70    ///1: Medium speed / medium power
71    MediumSpeed = 1,
72    ///3: Low speed / ultra-low power
73    LowSpeed = 3,
74}
75impl From<PWRMODE> for u8 {
76    #[inline(always)]
77    fn from(variant: PWRMODE) -> Self {
78        variant as _
79    }
80}
81impl crate::FieldSpec for PWRMODE {
82    type Ux = u8;
83}
84impl crate::IsEnum for PWRMODE {}
85///Field `PWRMODE` reader - Power Mode of the comparator 1
86pub type PWRMODE_R = crate::FieldReader<PWRMODE>;
87impl PWRMODE_R {
88    ///Get enumerated values variant
89    #[inline(always)]
90    pub const fn variant(&self) -> Option<PWRMODE> {
91        match self.bits {
92            0 => Some(PWRMODE::HighSpeed),
93            1 => Some(PWRMODE::MediumSpeed),
94            3 => Some(PWRMODE::LowSpeed),
95            _ => None,
96        }
97    }
98    ///High speed / full power
99    #[inline(always)]
100    pub fn is_high_speed(&self) -> bool {
101        *self == PWRMODE::HighSpeed
102    }
103    ///Medium speed / medium power
104    #[inline(always)]
105    pub fn is_medium_speed(&self) -> bool {
106        *self == PWRMODE::MediumSpeed
107    }
108    ///Low speed / ultra-low power
109    #[inline(always)]
110    pub fn is_low_speed(&self) -> bool {
111        *self == PWRMODE::LowSpeed
112    }
113}
114///Field `PWRMODE` writer - Power Mode of the comparator 1
115pub type PWRMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PWRMODE>;
116impl<'a, REG> PWRMODE_W<'a, REG>
117where
118    REG: crate::Writable + crate::RegisterSpec,
119    REG::Ux: From<u8>,
120{
121    ///High speed / full power
122    #[inline(always)]
123    pub fn high_speed(self) -> &'a mut crate::W<REG> {
124        self.variant(PWRMODE::HighSpeed)
125    }
126    ///Medium speed / medium power
127    #[inline(always)]
128    pub fn medium_speed(self) -> &'a mut crate::W<REG> {
129        self.variant(PWRMODE::MediumSpeed)
130    }
131    ///Low speed / ultra-low power
132    #[inline(always)]
133    pub fn low_speed(self) -> &'a mut crate::W<REG> {
134        self.variant(PWRMODE::LowSpeed)
135    }
136}
137/**Comparator 1 Input Minus connection configuration bit
138
139Value on reset: 0*/
140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142#[repr(u8)]
143pub enum INMSEL {
144    ///0: 1/4 of VRefint
145    OneQuarterVref = 0,
146    ///1: 1/2 of VRefint
147    OneHalfVref = 1,
148    ///2: 3/4 of VRefint
149    ThreeQuarterVref = 2,
150    ///3: VRefint
151    Vref = 3,
152    ///4: DAC Channel 1
153    DacCh1 = 4,
154    ///5: DAC Channel 2
155    DacCh2 = 5,
156    ///6: GPIO selected with INMESEL
157    Gpiox = 6,
158}
159impl From<INMSEL> for u8 {
160    #[inline(always)]
161    fn from(variant: INMSEL) -> Self {
162        variant as _
163    }
164}
165impl crate::FieldSpec for INMSEL {
166    type Ux = u8;
167}
168impl crate::IsEnum for INMSEL {}
169///Field `INMSEL` reader - Comparator 1 Input Minus connection configuration bit
170pub type INMSEL_R = crate::FieldReader<INMSEL>;
171impl INMSEL_R {
172    ///Get enumerated values variant
173    #[inline(always)]
174    pub const fn variant(&self) -> Option<INMSEL> {
175        match self.bits {
176            0 => Some(INMSEL::OneQuarterVref),
177            1 => Some(INMSEL::OneHalfVref),
178            2 => Some(INMSEL::ThreeQuarterVref),
179            3 => Some(INMSEL::Vref),
180            4 => Some(INMSEL::DacCh1),
181            5 => Some(INMSEL::DacCh2),
182            6 => Some(INMSEL::Gpiox),
183            _ => None,
184        }
185    }
186    ///1/4 of VRefint
187    #[inline(always)]
188    pub fn is_one_quarter_vref(&self) -> bool {
189        *self == INMSEL::OneQuarterVref
190    }
191    ///1/2 of VRefint
192    #[inline(always)]
193    pub fn is_one_half_vref(&self) -> bool {
194        *self == INMSEL::OneHalfVref
195    }
196    ///3/4 of VRefint
197    #[inline(always)]
198    pub fn is_three_quarter_vref(&self) -> bool {
199        *self == INMSEL::ThreeQuarterVref
200    }
201    ///VRefint
202    #[inline(always)]
203    pub fn is_vref(&self) -> bool {
204        *self == INMSEL::Vref
205    }
206    ///DAC Channel 1
207    #[inline(always)]
208    pub fn is_dac_ch1(&self) -> bool {
209        *self == INMSEL::DacCh1
210    }
211    ///DAC Channel 2
212    #[inline(always)]
213    pub fn is_dac_ch2(&self) -> bool {
214        *self == INMSEL::DacCh2
215    }
216    ///GPIO selected with INMESEL
217    #[inline(always)]
218    pub fn is_gpiox(&self) -> bool {
219        *self == INMSEL::Gpiox
220    }
221}
222///Field `INMSEL` writer - Comparator 1 Input Minus connection configuration bit
223pub type INMSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, INMSEL>;
224impl<'a, REG> INMSEL_W<'a, REG>
225where
226    REG: crate::Writable + crate::RegisterSpec,
227    REG::Ux: From<u8>,
228{
229    ///1/4 of VRefint
230    #[inline(always)]
231    pub fn one_quarter_vref(self) -> &'a mut crate::W<REG> {
232        self.variant(INMSEL::OneQuarterVref)
233    }
234    ///1/2 of VRefint
235    #[inline(always)]
236    pub fn one_half_vref(self) -> &'a mut crate::W<REG> {
237        self.variant(INMSEL::OneHalfVref)
238    }
239    ///3/4 of VRefint
240    #[inline(always)]
241    pub fn three_quarter_vref(self) -> &'a mut crate::W<REG> {
242        self.variant(INMSEL::ThreeQuarterVref)
243    }
244    ///VRefint
245    #[inline(always)]
246    pub fn vref(self) -> &'a mut crate::W<REG> {
247        self.variant(INMSEL::Vref)
248    }
249    ///DAC Channel 1
250    #[inline(always)]
251    pub fn dac_ch1(self) -> &'a mut crate::W<REG> {
252        self.variant(INMSEL::DacCh1)
253    }
254    ///DAC Channel 2
255    #[inline(always)]
256    pub fn dac_ch2(self) -> &'a mut crate::W<REG> {
257        self.variant(INMSEL::DacCh2)
258    }
259    ///GPIO selected with INMESEL
260    #[inline(always)]
261    pub fn gpiox(self) -> &'a mut crate::W<REG> {
262        self.variant(INMSEL::Gpiox)
263    }
264}
265/**Comparator1 input plus selection bit
266
267Value on reset: 0*/
268#[cfg_attr(feature = "defmt", derive(defmt::Format))]
269#[derive(Clone, Copy, Debug, PartialEq, Eq)]
270#[repr(u8)]
271pub enum INPSEL {
272    ///0: PC5 connected to input plus
273    Pc5 = 0,
274    ///1: PB2 connected to input plus
275    Pb2 = 1,
276    ///2: PA3 connected to input plus
277    Pa3 = 2,
278}
279impl From<INPSEL> for u8 {
280    #[inline(always)]
281    fn from(variant: INPSEL) -> Self {
282        variant as _
283    }
284}
285impl crate::FieldSpec for INPSEL {
286    type Ux = u8;
287}
288impl crate::IsEnum for INPSEL {}
289///Field `INPSEL` reader - Comparator1 input plus selection bit
290pub type INPSEL_R = crate::FieldReader<INPSEL>;
291impl INPSEL_R {
292    ///Get enumerated values variant
293    #[inline(always)]
294    pub const fn variant(&self) -> Option<INPSEL> {
295        match self.bits {
296            0 => Some(INPSEL::Pc5),
297            1 => Some(INPSEL::Pb2),
298            2 => Some(INPSEL::Pa3),
299            _ => None,
300        }
301    }
302    ///PC5 connected to input plus
303    #[inline(always)]
304    pub fn is_pc5(&self) -> bool {
305        *self == INPSEL::Pc5
306    }
307    ///PB2 connected to input plus
308    #[inline(always)]
309    pub fn is_pb2(&self) -> bool {
310        *self == INPSEL::Pb2
311    }
312    ///PA3 connected to input plus
313    #[inline(always)]
314    pub fn is_pa3(&self) -> bool {
315        *self == INPSEL::Pa3
316    }
317}
318///Field `INPSEL` writer - Comparator1 input plus selection bit
319pub type INPSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, INPSEL>;
320impl<'a, REG> INPSEL_W<'a, REG>
321where
322    REG: crate::Writable + crate::RegisterSpec,
323    REG::Ux: From<u8>,
324{
325    ///PC5 connected to input plus
326    #[inline(always)]
327    pub fn pc5(self) -> &'a mut crate::W<REG> {
328        self.variant(INPSEL::Pc5)
329    }
330    ///PB2 connected to input plus
331    #[inline(always)]
332    pub fn pb2(self) -> &'a mut crate::W<REG> {
333        self.variant(INPSEL::Pb2)
334    }
335    ///PA3 connected to input plus
336    #[inline(always)]
337    pub fn pa3(self) -> &'a mut crate::W<REG> {
338        self.variant(INPSEL::Pa3)
339    }
340}
341/**Comparator 1 polarity selection bit
342
343Value on reset: 0*/
344#[cfg_attr(feature = "defmt", derive(defmt::Format))]
345#[derive(Clone, Copy, Debug, PartialEq, Eq)]
346pub enum POLARITY {
347    ///0: Output is not inverted
348    NotInverted = 0,
349    ///1: Output is inverted
350    Inverted = 1,
351}
352impl From<POLARITY> for bool {
353    #[inline(always)]
354    fn from(variant: POLARITY) -> Self {
355        variant as u8 != 0
356    }
357}
358///Field `POLARITY` reader - Comparator 1 polarity selection bit
359pub type POLARITY_R = crate::BitReader<POLARITY>;
360impl POLARITY_R {
361    ///Get enumerated values variant
362    #[inline(always)]
363    pub const fn variant(&self) -> POLARITY {
364        match self.bits {
365            false => POLARITY::NotInverted,
366            true => POLARITY::Inverted,
367        }
368    }
369    ///Output is not inverted
370    #[inline(always)]
371    pub fn is_not_inverted(&self) -> bool {
372        *self == POLARITY::NotInverted
373    }
374    ///Output is inverted
375    #[inline(always)]
376    pub fn is_inverted(&self) -> bool {
377        *self == POLARITY::Inverted
378    }
379}
380///Field `POLARITY` writer - Comparator 1 polarity selection bit
381pub type POLARITY_W<'a, REG> = crate::BitWriter<'a, REG, POLARITY>;
382impl<'a, REG> POLARITY_W<'a, REG>
383where
384    REG: crate::Writable + crate::RegisterSpec,
385{
386    ///Output is not inverted
387    #[inline(always)]
388    pub fn not_inverted(self) -> &'a mut crate::W<REG> {
389        self.variant(POLARITY::NotInverted)
390    }
391    ///Output is inverted
392    #[inline(always)]
393    pub fn inverted(self) -> &'a mut crate::W<REG> {
394        self.variant(POLARITY::Inverted)
395    }
396}
397/**Comparator 1 hysteresis selection bits
398
399Value on reset: 0*/
400#[cfg_attr(feature = "defmt", derive(defmt::Format))]
401#[derive(Clone, Copy, Debug, PartialEq, Eq)]
402#[repr(u8)]
403pub enum HYST {
404    ///0: No hysteresis
405    NoHysteresis = 0,
406    ///1: Low hysteresis
407    LowHysteresis = 1,
408    ///2: Medium hysteresis
409    MediumHysteresis = 2,
410    ///3: High hysteresis
411    HighHysteresis = 3,
412}
413impl From<HYST> for u8 {
414    #[inline(always)]
415    fn from(variant: HYST) -> Self {
416        variant as _
417    }
418}
419impl crate::FieldSpec for HYST {
420    type Ux = u8;
421}
422impl crate::IsEnum for HYST {}
423///Field `HYST` reader - Comparator 1 hysteresis selection bits
424pub type HYST_R = crate::FieldReader<HYST>;
425impl HYST_R {
426    ///Get enumerated values variant
427    #[inline(always)]
428    pub const fn variant(&self) -> HYST {
429        match self.bits {
430            0 => HYST::NoHysteresis,
431            1 => HYST::LowHysteresis,
432            2 => HYST::MediumHysteresis,
433            3 => HYST::HighHysteresis,
434            _ => unreachable!(),
435        }
436    }
437    ///No hysteresis
438    #[inline(always)]
439    pub fn is_no_hysteresis(&self) -> bool {
440        *self == HYST::NoHysteresis
441    }
442    ///Low hysteresis
443    #[inline(always)]
444    pub fn is_low_hysteresis(&self) -> bool {
445        *self == HYST::LowHysteresis
446    }
447    ///Medium hysteresis
448    #[inline(always)]
449    pub fn is_medium_hysteresis(&self) -> bool {
450        *self == HYST::MediumHysteresis
451    }
452    ///High hysteresis
453    #[inline(always)]
454    pub fn is_high_hysteresis(&self) -> bool {
455        *self == HYST::HighHysteresis
456    }
457}
458///Field `HYST` writer - Comparator 1 hysteresis selection bits
459pub type HYST_W<'a, REG> = crate::FieldWriter<'a, REG, 2, HYST, crate::Safe>;
460impl<'a, REG> HYST_W<'a, REG>
461where
462    REG: crate::Writable + crate::RegisterSpec,
463    REG::Ux: From<u8>,
464{
465    ///No hysteresis
466    #[inline(always)]
467    pub fn no_hysteresis(self) -> &'a mut crate::W<REG> {
468        self.variant(HYST::NoHysteresis)
469    }
470    ///Low hysteresis
471    #[inline(always)]
472    pub fn low_hysteresis(self) -> &'a mut crate::W<REG> {
473        self.variant(HYST::LowHysteresis)
474    }
475    ///Medium hysteresis
476    #[inline(always)]
477    pub fn medium_hysteresis(self) -> &'a mut crate::W<REG> {
478        self.variant(HYST::MediumHysteresis)
479    }
480    ///High hysteresis
481    #[inline(always)]
482    pub fn high_hysteresis(self) -> &'a mut crate::W<REG> {
483        self.variant(HYST::HighHysteresis)
484    }
485}
486/**Comparator 1 blanking source selection bits
487
488Value on reset: 0*/
489#[cfg_attr(feature = "defmt", derive(defmt::Format))]
490#[derive(Clone, Copy, Debug, PartialEq, Eq)]
491#[repr(u8)]
492pub enum BLANKING {
493    ///0: No blanking
494    NoBlanking = 0,
495    ///4: TIM15 OC1 selected as blanking source
496    Tim1oc5 = 4,
497}
498impl From<BLANKING> for u8 {
499    #[inline(always)]
500    fn from(variant: BLANKING) -> Self {
501        variant as _
502    }
503}
504impl crate::FieldSpec for BLANKING {
505    type Ux = u8;
506}
507impl crate::IsEnum for BLANKING {}
508///Field `BLANKING` reader - Comparator 1 blanking source selection bits
509pub type BLANKING_R = crate::FieldReader<BLANKING>;
510impl BLANKING_R {
511    ///Get enumerated values variant
512    #[inline(always)]
513    pub const fn variant(&self) -> Option<BLANKING> {
514        match self.bits {
515            0 => Some(BLANKING::NoBlanking),
516            4 => Some(BLANKING::Tim1oc5),
517            _ => None,
518        }
519    }
520    ///No blanking
521    #[inline(always)]
522    pub fn is_no_blanking(&self) -> bool {
523        *self == BLANKING::NoBlanking
524    }
525    ///TIM15 OC1 selected as blanking source
526    #[inline(always)]
527    pub fn is_tim1oc5(&self) -> bool {
528        *self == BLANKING::Tim1oc5
529    }
530}
531///Field `BLANKING` writer - Comparator 1 blanking source selection bits
532pub type BLANKING_W<'a, REG> = crate::FieldWriter<'a, REG, 3, BLANKING>;
533impl<'a, REG> BLANKING_W<'a, REG>
534where
535    REG: crate::Writable + crate::RegisterSpec,
536    REG::Ux: From<u8>,
537{
538    ///No blanking
539    #[inline(always)]
540    pub fn no_blanking(self) -> &'a mut crate::W<REG> {
541        self.variant(BLANKING::NoBlanking)
542    }
543    ///TIM15 OC1 selected as blanking source
544    #[inline(always)]
545    pub fn tim1oc5(self) -> &'a mut crate::W<REG> {
546        self.variant(BLANKING::Tim1oc5)
547    }
548}
549/**Scaler bridge enable
550
551Value on reset: 0*/
552#[cfg_attr(feature = "defmt", derive(defmt::Format))]
553#[derive(Clone, Copy, Debug, PartialEq, Eq)]
554pub enum BRGEN {
555    ///0: Scaler resistor bridge disabled
556    Disabled = 0,
557    ///1: Scaler resistor bridge enabled
558    Enabled = 1,
559}
560impl From<BRGEN> for bool {
561    #[inline(always)]
562    fn from(variant: BRGEN) -> Self {
563        variant as u8 != 0
564    }
565}
566///Field `BRGEN` reader - Scaler bridge enable
567pub type BRGEN_R = crate::BitReader<BRGEN>;
568impl BRGEN_R {
569    ///Get enumerated values variant
570    #[inline(always)]
571    pub const fn variant(&self) -> BRGEN {
572        match self.bits {
573            false => BRGEN::Disabled,
574            true => BRGEN::Enabled,
575        }
576    }
577    ///Scaler resistor bridge disabled
578    #[inline(always)]
579    pub fn is_disabled(&self) -> bool {
580        *self == BRGEN::Disabled
581    }
582    ///Scaler resistor bridge enabled
583    #[inline(always)]
584    pub fn is_enabled(&self) -> bool {
585        *self == BRGEN::Enabled
586    }
587}
588///Field `BRGEN` writer - Scaler bridge enable
589pub type BRGEN_W<'a, REG> = crate::BitWriter<'a, REG, BRGEN>;
590impl<'a, REG> BRGEN_W<'a, REG>
591where
592    REG: crate::Writable + crate::RegisterSpec,
593{
594    ///Scaler resistor bridge disabled
595    #[inline(always)]
596    pub fn disabled(self) -> &'a mut crate::W<REG> {
597        self.variant(BRGEN::Disabled)
598    }
599    ///Scaler resistor bridge enabled
600    #[inline(always)]
601    pub fn enabled(self) -> &'a mut crate::W<REG> {
602        self.variant(BRGEN::Enabled)
603    }
604}
605/**Voltage scaler enable bit
606
607Value on reset: 0*/
608#[cfg_attr(feature = "defmt", derive(defmt::Format))]
609#[derive(Clone, Copy, Debug, PartialEq, Eq)]
610pub enum SCALEN {
611    ///0: Voltage scaler disabled
612    Disabled = 0,
613    ///1: Voltage scaler enabled
614    Enabled = 1,
615}
616impl From<SCALEN> for bool {
617    #[inline(always)]
618    fn from(variant: SCALEN) -> Self {
619        variant as u8 != 0
620    }
621}
622///Field `SCALEN` reader - Voltage scaler enable bit
623pub type SCALEN_R = crate::BitReader<SCALEN>;
624impl SCALEN_R {
625    ///Get enumerated values variant
626    #[inline(always)]
627    pub const fn variant(&self) -> SCALEN {
628        match self.bits {
629            false => SCALEN::Disabled,
630            true => SCALEN::Enabled,
631        }
632    }
633    ///Voltage scaler disabled
634    #[inline(always)]
635    pub fn is_disabled(&self) -> bool {
636        *self == SCALEN::Disabled
637    }
638    ///Voltage scaler enabled
639    #[inline(always)]
640    pub fn is_enabled(&self) -> bool {
641        *self == SCALEN::Enabled
642    }
643}
644///Field `SCALEN` writer - Voltage scaler enable bit
645pub type SCALEN_W<'a, REG> = crate::BitWriter<'a, REG, SCALEN>;
646impl<'a, REG> SCALEN_W<'a, REG>
647where
648    REG: crate::Writable + crate::RegisterSpec,
649{
650    ///Voltage scaler disabled
651    #[inline(always)]
652    pub fn disabled(self) -> &'a mut crate::W<REG> {
653        self.variant(SCALEN::Disabled)
654    }
655    ///Voltage scaler enabled
656    #[inline(always)]
657    pub fn enabled(self) -> &'a mut crate::W<REG> {
658        self.variant(SCALEN::Enabled)
659    }
660}
661/**comparator 1 input minus extended selection bits
662
663Value on reset: 0*/
664#[cfg_attr(feature = "defmt", derive(defmt::Format))]
665#[derive(Clone, Copy, Debug, PartialEq, Eq)]
666#[repr(u8)]
667pub enum INMESEL {
668    ///0: PC4
669    Pc4 = 0,
670    ///1: PA0
671    Pa0 = 1,
672    ///2: PA4
673    Pa4 = 2,
674    ///3: PA5
675    Pa5 = 3,
676}
677impl From<INMESEL> for u8 {
678    #[inline(always)]
679    fn from(variant: INMESEL) -> Self {
680        variant as _
681    }
682}
683impl crate::FieldSpec for INMESEL {
684    type Ux = u8;
685}
686impl crate::IsEnum for INMESEL {}
687///Field `INMESEL` reader - comparator 1 input minus extended selection bits
688pub type INMESEL_R = crate::FieldReader<INMESEL>;
689impl INMESEL_R {
690    ///Get enumerated values variant
691    #[inline(always)]
692    pub const fn variant(&self) -> INMESEL {
693        match self.bits {
694            0 => INMESEL::Pc4,
695            1 => INMESEL::Pa0,
696            2 => INMESEL::Pa4,
697            3 => INMESEL::Pa5,
698            _ => unreachable!(),
699        }
700    }
701    ///PC4
702    #[inline(always)]
703    pub fn is_pc4(&self) -> bool {
704        *self == INMESEL::Pc4
705    }
706    ///PA0
707    #[inline(always)]
708    pub fn is_pa0(&self) -> bool {
709        *self == INMESEL::Pa0
710    }
711    ///PA4
712    #[inline(always)]
713    pub fn is_pa4(&self) -> bool {
714        *self == INMESEL::Pa4
715    }
716    ///PA5
717    #[inline(always)]
718    pub fn is_pa5(&self) -> bool {
719        *self == INMESEL::Pa5
720    }
721}
722///Field `INMESEL` writer - comparator 1 input minus extended selection bits
723pub type INMESEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, INMESEL, crate::Safe>;
724impl<'a, REG> INMESEL_W<'a, REG>
725where
726    REG: crate::Writable + crate::RegisterSpec,
727    REG::Ux: From<u8>,
728{
729    ///PC4
730    #[inline(always)]
731    pub fn pc4(self) -> &'a mut crate::W<REG> {
732        self.variant(INMESEL::Pc4)
733    }
734    ///PA0
735    #[inline(always)]
736    pub fn pa0(self) -> &'a mut crate::W<REG> {
737        self.variant(INMESEL::Pa0)
738    }
739    ///PA4
740    #[inline(always)]
741    pub fn pa4(self) -> &'a mut crate::W<REG> {
742        self.variant(INMESEL::Pa4)
743    }
744    ///PA5
745    #[inline(always)]
746    pub fn pa5(self) -> &'a mut crate::W<REG> {
747        self.variant(INMESEL::Pa5)
748    }
749}
750/**Comparator 1 output status bit
751
752Value on reset: 0*/
753#[cfg_attr(feature = "defmt", derive(defmt::Format))]
754#[derive(Clone, Copy, Debug, PartialEq, Eq)]
755pub enum VALUE {
756    ///0: Comparator output is low
757    Low = 0,
758    ///1: Comparator output is high
759    High = 1,
760}
761impl From<VALUE> for bool {
762    #[inline(always)]
763    fn from(variant: VALUE) -> Self {
764        variant as u8 != 0
765    }
766}
767///Field `VALUE` reader - Comparator 1 output status bit
768pub type VALUE_R = crate::BitReader<VALUE>;
769impl VALUE_R {
770    ///Get enumerated values variant
771    #[inline(always)]
772    pub const fn variant(&self) -> VALUE {
773        match self.bits {
774            false => VALUE::Low,
775            true => VALUE::High,
776        }
777    }
778    ///Comparator output is low
779    #[inline(always)]
780    pub fn is_low(&self) -> bool {
781        *self == VALUE::Low
782    }
783    ///Comparator output is high
784    #[inline(always)]
785    pub fn is_high(&self) -> bool {
786        *self == VALUE::High
787    }
788}
789///Field `LOCK` writer - COMP1_CSR register lock bit
790pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
791impl R {
792    ///Bit 0 - Comparator 1 enable bit
793    #[inline(always)]
794    pub fn en(&self) -> EN_R {
795        EN_R::new((self.bits & 1) != 0)
796    }
797    ///Bits 2:3 - Power Mode of the comparator 1
798    #[inline(always)]
799    pub fn pwrmode(&self) -> PWRMODE_R {
800        PWRMODE_R::new(((self.bits >> 2) & 3) as u8)
801    }
802    ///Bits 4:6 - Comparator 1 Input Minus connection configuration bit
803    #[inline(always)]
804    pub fn inmsel(&self) -> INMSEL_R {
805        INMSEL_R::new(((self.bits >> 4) & 7) as u8)
806    }
807    ///Bits 7:8 - Comparator1 input plus selection bit
808    #[inline(always)]
809    pub fn inpsel(&self) -> INPSEL_R {
810        INPSEL_R::new(((self.bits >> 7) & 3) as u8)
811    }
812    ///Bit 15 - Comparator 1 polarity selection bit
813    #[inline(always)]
814    pub fn polarity(&self) -> POLARITY_R {
815        POLARITY_R::new(((self.bits >> 15) & 1) != 0)
816    }
817    ///Bits 16:17 - Comparator 1 hysteresis selection bits
818    #[inline(always)]
819    pub fn hyst(&self) -> HYST_R {
820        HYST_R::new(((self.bits >> 16) & 3) as u8)
821    }
822    ///Bits 18:20 - Comparator 1 blanking source selection bits
823    #[inline(always)]
824    pub fn blanking(&self) -> BLANKING_R {
825        BLANKING_R::new(((self.bits >> 18) & 7) as u8)
826    }
827    ///Bit 22 - Scaler bridge enable
828    #[inline(always)]
829    pub fn brgen(&self) -> BRGEN_R {
830        BRGEN_R::new(((self.bits >> 22) & 1) != 0)
831    }
832    ///Bit 23 - Voltage scaler enable bit
833    #[inline(always)]
834    pub fn scalen(&self) -> SCALEN_R {
835        SCALEN_R::new(((self.bits >> 23) & 1) != 0)
836    }
837    ///Bits 25:26 - comparator 1 input minus extended selection bits
838    #[inline(always)]
839    pub fn inmesel(&self) -> INMESEL_R {
840        INMESEL_R::new(((self.bits >> 25) & 3) as u8)
841    }
842    ///Bit 30 - Comparator 1 output status bit
843    #[inline(always)]
844    pub fn value(&self) -> VALUE_R {
845        VALUE_R::new(((self.bits >> 30) & 1) != 0)
846    }
847}
848impl core::fmt::Debug for R {
849    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
850        f.debug_struct("COMP1_CSR")
851            .field("en", &self.en())
852            .field("pwrmode", &self.pwrmode())
853            .field("inmsel", &self.inmsel())
854            .field("inpsel", &self.inpsel())
855            .field("polarity", &self.polarity())
856            .field("hyst", &self.hyst())
857            .field("blanking", &self.blanking())
858            .field("brgen", &self.brgen())
859            .field("scalen", &self.scalen())
860            .field("inmesel", &self.inmesel())
861            .field("value", &self.value())
862            .finish()
863    }
864}
865impl W {
866    ///Bit 0 - Comparator 1 enable bit
867    #[inline(always)]
868    pub fn en(&mut self) -> EN_W<COMP1_CSRrs> {
869        EN_W::new(self, 0)
870    }
871    ///Bits 2:3 - Power Mode of the comparator 1
872    #[inline(always)]
873    pub fn pwrmode(&mut self) -> PWRMODE_W<COMP1_CSRrs> {
874        PWRMODE_W::new(self, 2)
875    }
876    ///Bits 4:6 - Comparator 1 Input Minus connection configuration bit
877    #[inline(always)]
878    pub fn inmsel(&mut self) -> INMSEL_W<COMP1_CSRrs> {
879        INMSEL_W::new(self, 4)
880    }
881    ///Bits 7:8 - Comparator1 input plus selection bit
882    #[inline(always)]
883    pub fn inpsel(&mut self) -> INPSEL_W<COMP1_CSRrs> {
884        INPSEL_W::new(self, 7)
885    }
886    ///Bit 15 - Comparator 1 polarity selection bit
887    #[inline(always)]
888    pub fn polarity(&mut self) -> POLARITY_W<COMP1_CSRrs> {
889        POLARITY_W::new(self, 15)
890    }
891    ///Bits 16:17 - Comparator 1 hysteresis selection bits
892    #[inline(always)]
893    pub fn hyst(&mut self) -> HYST_W<COMP1_CSRrs> {
894        HYST_W::new(self, 16)
895    }
896    ///Bits 18:20 - Comparator 1 blanking source selection bits
897    #[inline(always)]
898    pub fn blanking(&mut self) -> BLANKING_W<COMP1_CSRrs> {
899        BLANKING_W::new(self, 18)
900    }
901    ///Bit 22 - Scaler bridge enable
902    #[inline(always)]
903    pub fn brgen(&mut self) -> BRGEN_W<COMP1_CSRrs> {
904        BRGEN_W::new(self, 22)
905    }
906    ///Bit 23 - Voltage scaler enable bit
907    #[inline(always)]
908    pub fn scalen(&mut self) -> SCALEN_W<COMP1_CSRrs> {
909        SCALEN_W::new(self, 23)
910    }
911    ///Bits 25:26 - comparator 1 input minus extended selection bits
912    #[inline(always)]
913    pub fn inmesel(&mut self) -> INMESEL_W<COMP1_CSRrs> {
914        INMESEL_W::new(self, 25)
915    }
916    ///Bit 31 - COMP1_CSR register lock bit
917    #[inline(always)]
918    pub fn lock(&mut self) -> LOCK_W<COMP1_CSRrs> {
919        LOCK_W::new(self, 31)
920    }
921}
922/**Comparator 1 control and status register
923
924You can [`read`](crate::Reg::read) this register and get [`comp1_csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`comp1_csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
925
926See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#COMP:COMP1_CSR)*/
927pub struct COMP1_CSRrs;
928impl crate::RegisterSpec for COMP1_CSRrs {
929    type Ux = u32;
930}
931///`read()` method returns [`comp1_csr::R`](R) reader structure
932impl crate::Readable for COMP1_CSRrs {}
933///`write(|w| ..)` method takes [`comp1_csr::W`](W) writer structure
934impl crate::Writable for COMP1_CSRrs {
935    type Safety = crate::Unsafe;
936}
937///`reset()` method sets COMP1_CSR to value 0
938impl crate::Resettable for COMP1_CSRrs {}
stm32l4/stm32l4x1/comp/comp1_csr.rs

stm32l4/stm32l4x1/comp/
comp1_csr.rs
