stm32l4/stm32l4x1/adc1/
cfgr2.rs

1///Register `CFGR2` reader
2pub type R = crate::R<CFGR2rs>;
3///Register `CFGR2` writer
4pub type W = crate::W<CFGR2rs>;
5/**DMAEN
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum ROVSE {
11    ///0: Regular Oversampling disabled
12    Disabled = 0,
13    ///1: Regular Oversampling enabled
14    Enabled = 1,
15}
16impl From<ROVSE> for bool {
17    #[inline(always)]
18    fn from(variant: ROVSE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `ROVSE` reader - DMAEN
23pub type ROVSE_R = crate::BitReader<ROVSE>;
24impl ROVSE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> ROVSE {
28        match self.bits {
29            false => ROVSE::Disabled,
30            true => ROVSE::Enabled,
31        }
32    }
33    ///Regular Oversampling disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == ROVSE::Disabled
37    }
38    ///Regular Oversampling enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == ROVSE::Enabled
42    }
43}
44///Field `ROVSE` writer - DMAEN
45pub type ROVSE_W<'a, REG> = crate::BitWriter<'a, REG, ROVSE>;
46impl<'a, REG> ROVSE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Regular Oversampling disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(ROVSE::Disabled)
54    }
55    ///Regular Oversampling enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(ROVSE::Enabled)
59    }
60}
61/**DMACFG
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum JOVSE {
67    ///0: Injected Oversampling disabled
68    Disabled = 0,
69    ///1: Injected Oversampling enabled
70    Enabled = 1,
71}
72impl From<JOVSE> for bool {
73    #[inline(always)]
74    fn from(variant: JOVSE) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `JOVSE` reader - DMACFG
79pub type JOVSE_R = crate::BitReader<JOVSE>;
80impl JOVSE_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> JOVSE {
84        match self.bits {
85            false => JOVSE::Disabled,
86            true => JOVSE::Enabled,
87        }
88    }
89    ///Injected Oversampling disabled
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == JOVSE::Disabled
93    }
94    ///Injected Oversampling enabled
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == JOVSE::Enabled
98    }
99}
100///Field `JOVSE` writer - DMACFG
101pub type JOVSE_W<'a, REG> = crate::BitWriter<'a, REG, JOVSE>;
102impl<'a, REG> JOVSE_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Injected Oversampling disabled
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(JOVSE::Disabled)
110    }
111    ///Injected Oversampling enabled
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(JOVSE::Enabled)
115    }
116}
117/**RES
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122#[repr(u8)]
123pub enum OVSR {
124    ///0: 2x
125    Ratio2 = 0,
126    ///1: 4x
127    Ratio4 = 1,
128    ///2: 8x
129    Ratio8 = 2,
130    ///3: 16x
131    Ratio16 = 3,
132    ///4: 32x
133    Ratio32 = 4,
134    ///5: 64x
135    Ratio64 = 5,
136    ///6: 128x
137    Ratio128 = 6,
138    ///7: 256x
139    Ratio256 = 7,
140}
141impl From<OVSR> for u8 {
142    #[inline(always)]
143    fn from(variant: OVSR) -> Self {
144        variant as _
145    }
146}
147impl crate::FieldSpec for OVSR {
148    type Ux = u8;
149}
150impl crate::IsEnum for OVSR {}
151///Field `OVSR` reader - RES
152pub type OVSR_R = crate::FieldReader<OVSR>;
153impl OVSR_R {
154    ///Get enumerated values variant
155    #[inline(always)]
156    pub const fn variant(&self) -> OVSR {
157        match self.bits {
158            0 => OVSR::Ratio2,
159            1 => OVSR::Ratio4,
160            2 => OVSR::Ratio8,
161            3 => OVSR::Ratio16,
162            4 => OVSR::Ratio32,
163            5 => OVSR::Ratio64,
164            6 => OVSR::Ratio128,
165            7 => OVSR::Ratio256,
166            _ => unreachable!(),
167        }
168    }
169    ///2x
170    #[inline(always)]
171    pub fn is_ratio2(&self) -> bool {
172        *self == OVSR::Ratio2
173    }
174    ///4x
175    #[inline(always)]
176    pub fn is_ratio4(&self) -> bool {
177        *self == OVSR::Ratio4
178    }
179    ///8x
180    #[inline(always)]
181    pub fn is_ratio8(&self) -> bool {
182        *self == OVSR::Ratio8
183    }
184    ///16x
185    #[inline(always)]
186    pub fn is_ratio16(&self) -> bool {
187        *self == OVSR::Ratio16
188    }
189    ///32x
190    #[inline(always)]
191    pub fn is_ratio32(&self) -> bool {
192        *self == OVSR::Ratio32
193    }
194    ///64x
195    #[inline(always)]
196    pub fn is_ratio64(&self) -> bool {
197        *self == OVSR::Ratio64
198    }
199    ///128x
200    #[inline(always)]
201    pub fn is_ratio128(&self) -> bool {
202        *self == OVSR::Ratio128
203    }
204    ///256x
205    #[inline(always)]
206    pub fn is_ratio256(&self) -> bool {
207        *self == OVSR::Ratio256
208    }
209}
210///Field `OVSR` writer - RES
211pub type OVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 3, OVSR, crate::Safe>;
212impl<'a, REG> OVSR_W<'a, REG>
213where
214    REG: crate::Writable + crate::RegisterSpec,
215    REG::Ux: From<u8>,
216{
217    ///2x
218    #[inline(always)]
219    pub fn ratio2(self) -> &'a mut crate::W<REG> {
220        self.variant(OVSR::Ratio2)
221    }
222    ///4x
223    #[inline(always)]
224    pub fn ratio4(self) -> &'a mut crate::W<REG> {
225        self.variant(OVSR::Ratio4)
226    }
227    ///8x
228    #[inline(always)]
229    pub fn ratio8(self) -> &'a mut crate::W<REG> {
230        self.variant(OVSR::Ratio8)
231    }
232    ///16x
233    #[inline(always)]
234    pub fn ratio16(self) -> &'a mut crate::W<REG> {
235        self.variant(OVSR::Ratio16)
236    }
237    ///32x
238    #[inline(always)]
239    pub fn ratio32(self) -> &'a mut crate::W<REG> {
240        self.variant(OVSR::Ratio32)
241    }
242    ///64x
243    #[inline(always)]
244    pub fn ratio64(self) -> &'a mut crate::W<REG> {
245        self.variant(OVSR::Ratio64)
246    }
247    ///128x
248    #[inline(always)]
249    pub fn ratio128(self) -> &'a mut crate::W<REG> {
250        self.variant(OVSR::Ratio128)
251    }
252    ///256x
253    #[inline(always)]
254    pub fn ratio256(self) -> &'a mut crate::W<REG> {
255        self.variant(OVSR::Ratio256)
256    }
257}
258/**ALIGN
259
260Value on reset: 0*/
261#[cfg_attr(feature = "defmt", derive(defmt::Format))]
262#[derive(Clone, Copy, Debug, PartialEq, Eq)]
263#[repr(u8)]
264pub enum OVSS {
265    ///0: No Shift
266    NoShift = 0,
267    ///1: Shift 1-bit
268    Shift1bit = 1,
269    ///2: Shift 2-bit
270    Shift2bit = 2,
271    ///3: Shift 3-bit
272    Shift3bit = 3,
273    ///4: Shift 4-bit
274    Shift4bit = 4,
275    ///5: Shift 5-bit
276    Shift5bit = 5,
277    ///6: Shift 6-bit
278    Shift6bit = 6,
279    ///7: Shift 7-bit
280    Shift7bit = 7,
281    ///8: Shift 8-bit
282    Shift8bit = 8,
283}
284impl From<OVSS> for u8 {
285    #[inline(always)]
286    fn from(variant: OVSS) -> Self {
287        variant as _
288    }
289}
290impl crate::FieldSpec for OVSS {
291    type Ux = u8;
292}
293impl crate::IsEnum for OVSS {}
294///Field `OVSS` reader - ALIGN
295pub type OVSS_R = crate::FieldReader<OVSS>;
296impl OVSS_R {
297    ///Get enumerated values variant
298    #[inline(always)]
299    pub const fn variant(&self) -> Option<OVSS> {
300        match self.bits {
301            0 => Some(OVSS::NoShift),
302            1 => Some(OVSS::Shift1bit),
303            2 => Some(OVSS::Shift2bit),
304            3 => Some(OVSS::Shift3bit),
305            4 => Some(OVSS::Shift4bit),
306            5 => Some(OVSS::Shift5bit),
307            6 => Some(OVSS::Shift6bit),
308            7 => Some(OVSS::Shift7bit),
309            8 => Some(OVSS::Shift8bit),
310            _ => None,
311        }
312    }
313    ///No Shift
314    #[inline(always)]
315    pub fn is_no_shift(&self) -> bool {
316        *self == OVSS::NoShift
317    }
318    ///Shift 1-bit
319    #[inline(always)]
320    pub fn is_shift1bit(&self) -> bool {
321        *self == OVSS::Shift1bit
322    }
323    ///Shift 2-bit
324    #[inline(always)]
325    pub fn is_shift2bit(&self) -> bool {
326        *self == OVSS::Shift2bit
327    }
328    ///Shift 3-bit
329    #[inline(always)]
330    pub fn is_shift3bit(&self) -> bool {
331        *self == OVSS::Shift3bit
332    }
333    ///Shift 4-bit
334    #[inline(always)]
335    pub fn is_shift4bit(&self) -> bool {
336        *self == OVSS::Shift4bit
337    }
338    ///Shift 5-bit
339    #[inline(always)]
340    pub fn is_shift5bit(&self) -> bool {
341        *self == OVSS::Shift5bit
342    }
343    ///Shift 6-bit
344    #[inline(always)]
345    pub fn is_shift6bit(&self) -> bool {
346        *self == OVSS::Shift6bit
347    }
348    ///Shift 7-bit
349    #[inline(always)]
350    pub fn is_shift7bit(&self) -> bool {
351        *self == OVSS::Shift7bit
352    }
353    ///Shift 8-bit
354    #[inline(always)]
355    pub fn is_shift8bit(&self) -> bool {
356        *self == OVSS::Shift8bit
357    }
358}
359///Field `OVSS` writer - ALIGN
360pub type OVSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4, OVSS>;
361impl<'a, REG> OVSS_W<'a, REG>
362where
363    REG: crate::Writable + crate::RegisterSpec,
364    REG::Ux: From<u8>,
365{
366    ///No Shift
367    #[inline(always)]
368    pub fn no_shift(self) -> &'a mut crate::W<REG> {
369        self.variant(OVSS::NoShift)
370    }
371    ///Shift 1-bit
372    #[inline(always)]
373    pub fn shift1bit(self) -> &'a mut crate::W<REG> {
374        self.variant(OVSS::Shift1bit)
375    }
376    ///Shift 2-bit
377    #[inline(always)]
378    pub fn shift2bit(self) -> &'a mut crate::W<REG> {
379        self.variant(OVSS::Shift2bit)
380    }
381    ///Shift 3-bit
382    #[inline(always)]
383    pub fn shift3bit(self) -> &'a mut crate::W<REG> {
384        self.variant(OVSS::Shift3bit)
385    }
386    ///Shift 4-bit
387    #[inline(always)]
388    pub fn shift4bit(self) -> &'a mut crate::W<REG> {
389        self.variant(OVSS::Shift4bit)
390    }
391    ///Shift 5-bit
392    #[inline(always)]
393    pub fn shift5bit(self) -> &'a mut crate::W<REG> {
394        self.variant(OVSS::Shift5bit)
395    }
396    ///Shift 6-bit
397    #[inline(always)]
398    pub fn shift6bit(self) -> &'a mut crate::W<REG> {
399        self.variant(OVSS::Shift6bit)
400    }
401    ///Shift 7-bit
402    #[inline(always)]
403    pub fn shift7bit(self) -> &'a mut crate::W<REG> {
404        self.variant(OVSS::Shift7bit)
405    }
406    ///Shift 8-bit
407    #[inline(always)]
408    pub fn shift8bit(self) -> &'a mut crate::W<REG> {
409        self.variant(OVSS::Shift8bit)
410    }
411}
412/**EXTSEL
413
414Value on reset: 0*/
415#[cfg_attr(feature = "defmt", derive(defmt::Format))]
416#[derive(Clone, Copy, Debug, PartialEq, Eq)]
417pub enum TOVS {
418    ///0: All oversampled conversions for a channel are done consecutively following a trigger
419    All = 0,
420    ///1: Each oversampled conversion for a channel needs a new trigger
421    Single = 1,
422}
423impl From<TOVS> for bool {
424    #[inline(always)]
425    fn from(variant: TOVS) -> Self {
426        variant as u8 != 0
427    }
428}
429///Field `TOVS` reader - EXTSEL
430pub type TOVS_R = crate::BitReader<TOVS>;
431impl TOVS_R {
432    ///Get enumerated values variant
433    #[inline(always)]
434    pub const fn variant(&self) -> TOVS {
435        match self.bits {
436            false => TOVS::All,
437            true => TOVS::Single,
438        }
439    }
440    ///All oversampled conversions for a channel are done consecutively following a trigger
441    #[inline(always)]
442    pub fn is_all(&self) -> bool {
443        *self == TOVS::All
444    }
445    ///Each oversampled conversion for a channel needs a new trigger
446    #[inline(always)]
447    pub fn is_single(&self) -> bool {
448        *self == TOVS::Single
449    }
450}
451///Field `TOVS` writer - EXTSEL
452pub type TOVS_W<'a, REG> = crate::BitWriter<'a, REG, TOVS>;
453impl<'a, REG> TOVS_W<'a, REG>
454where
455    REG: crate::Writable + crate::RegisterSpec,
456{
457    ///All oversampled conversions for a channel are done consecutively following a trigger
458    #[inline(always)]
459    pub fn all(self) -> &'a mut crate::W<REG> {
460        self.variant(TOVS::All)
461    }
462    ///Each oversampled conversion for a channel needs a new trigger
463    #[inline(always)]
464    pub fn single(self) -> &'a mut crate::W<REG> {
465        self.variant(TOVS::Single)
466    }
467}
468/**EXTEN
469
470Value on reset: 0*/
471#[cfg_attr(feature = "defmt", derive(defmt::Format))]
472#[derive(Clone, Copy, Debug, PartialEq, Eq)]
473pub enum ROVSM {
474    ///0: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
475    ContinuedMode = 0,
476    ///1: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)
477    ResumedMode = 1,
478}
479impl From<ROVSM> for bool {
480    #[inline(always)]
481    fn from(variant: ROVSM) -> Self {
482        variant as u8 != 0
483    }
484}
485///Field `ROVSM` reader - EXTEN
486pub type ROVSM_R = crate::BitReader<ROVSM>;
487impl ROVSM_R {
488    ///Get enumerated values variant
489    #[inline(always)]
490    pub const fn variant(&self) -> ROVSM {
491        match self.bits {
492            false => ROVSM::ContinuedMode,
493            true => ROVSM::ResumedMode,
494        }
495    }
496    ///When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
497    #[inline(always)]
498    pub fn is_continued_mode(&self) -> bool {
499        *self == ROVSM::ContinuedMode
500    }
501    ///When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)
502    #[inline(always)]
503    pub fn is_resumed_mode(&self) -> bool {
504        *self == ROVSM::ResumedMode
505    }
506}
507///Field `ROVSM` writer - EXTEN
508pub type ROVSM_W<'a, REG> = crate::BitWriter<'a, REG, ROVSM>;
509impl<'a, REG> ROVSM_W<'a, REG>
510where
511    REG: crate::Writable + crate::RegisterSpec,
512{
513    ///When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
514    #[inline(always)]
515    pub fn continued_mode(self) -> &'a mut crate::W<REG> {
516        self.variant(ROVSM::ContinuedMode)
517    }
518    ///When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)
519    #[inline(always)]
520    pub fn resumed_mode(self) -> &'a mut crate::W<REG> {
521        self.variant(ROVSM::ResumedMode)
522    }
523}
524impl R {
525    ///Bit 0 - DMAEN
526    #[inline(always)]
527    pub fn rovse(&self) -> ROVSE_R {
528        ROVSE_R::new((self.bits & 1) != 0)
529    }
530    ///Bit 1 - DMACFG
531    #[inline(always)]
532    pub fn jovse(&self) -> JOVSE_R {
533        JOVSE_R::new(((self.bits >> 1) & 1) != 0)
534    }
535    ///Bits 2:4 - RES
536    #[inline(always)]
537    pub fn ovsr(&self) -> OVSR_R {
538        OVSR_R::new(((self.bits >> 2) & 7) as u8)
539    }
540    ///Bits 5:8 - ALIGN
541    #[inline(always)]
542    pub fn ovss(&self) -> OVSS_R {
543        OVSS_R::new(((self.bits >> 5) & 0x0f) as u8)
544    }
545    ///Bit 9 - EXTSEL
546    #[inline(always)]
547    pub fn tovs(&self) -> TOVS_R {
548        TOVS_R::new(((self.bits >> 9) & 1) != 0)
549    }
550    ///Bit 10 - EXTEN
551    #[inline(always)]
552    pub fn rovsm(&self) -> ROVSM_R {
553        ROVSM_R::new(((self.bits >> 10) & 1) != 0)
554    }
555}
556impl core::fmt::Debug for R {
557    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
558        f.debug_struct("CFGR2")
559            .field("rovsm", &self.rovsm())
560            .field("tovs", &self.tovs())
561            .field("ovss", &self.ovss())
562            .field("ovsr", &self.ovsr())
563            .field("jovse", &self.jovse())
564            .field("rovse", &self.rovse())
565            .finish()
566    }
567}
568impl W {
569    ///Bit 0 - DMAEN
570    #[inline(always)]
571    pub fn rovse(&mut self) -> ROVSE_W<CFGR2rs> {
572        ROVSE_W::new(self, 0)
573    }
574    ///Bit 1 - DMACFG
575    #[inline(always)]
576    pub fn jovse(&mut self) -> JOVSE_W<CFGR2rs> {
577        JOVSE_W::new(self, 1)
578    }
579    ///Bits 2:4 - RES
580    #[inline(always)]
581    pub fn ovsr(&mut self) -> OVSR_W<CFGR2rs> {
582        OVSR_W::new(self, 2)
583    }
584    ///Bits 5:8 - ALIGN
585    #[inline(always)]
586    pub fn ovss(&mut self) -> OVSS_W<CFGR2rs> {
587        OVSS_W::new(self, 5)
588    }
589    ///Bit 9 - EXTSEL
590    #[inline(always)]
591    pub fn tovs(&mut self) -> TOVS_W<CFGR2rs> {
592        TOVS_W::new(self, 9)
593    }
594    ///Bit 10 - EXTEN
595    #[inline(always)]
596    pub fn rovsm(&mut self) -> ROVSM_W<CFGR2rs> {
597        ROVSM_W::new(self, 10)
598    }
599}
600/**configuration register
601
602You can [`read`](crate::Reg::read) this register and get [`cfgr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
603
604See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L4x1.html#ADC1:CFGR2)*/
605pub struct CFGR2rs;
606impl crate::RegisterSpec for CFGR2rs {
607    type Ux = u32;
608}
609///`read()` method returns [`cfgr2::R`](R) reader structure
610impl crate::Readable for CFGR2rs {}
611///`write(|w| ..)` method takes [`cfgr2::W`](W) writer structure
612impl crate::Writable for CFGR2rs {
613    type Safety = crate::Unsafe;
614}
615///`reset()` method sets CFGR2 to value 0
616impl crate::Resettable for CFGR2rs {}
stm32l4/stm32l4x1/adc1/cfgr2.rs

stm32l4/stm32l4x1/adc1/
cfgr2.rs
