Expand description
Digital filter for sigma delta modulators
Modules§
- awscd0r
- analog watchdog and short-circuit detector register
- awscd1r
- AWSCD1R
- awscd2r
- AWSCD2R
- awscd3r
- AWSCD3R
- awscd4r
- AWSCD4R
- awscd5r
- AWSCD5R
- awscd6r
- AWSCD6R
- awscd7r
- AWSCD7R
- chcfg0r1
- channel configuration y register
- chcfg0r2
- channel configuration y register
- chcfg1r1
- CHCFG1R1
- chcfg1r2
- CHCFG1R2
- chcfg2r1
- CHCFG2R1
- chcfg2r2
- CHCFG2R2
- chcfg3r1
- CHCFG3R1
- chcfg3r2
- CHCFG3R2
- chcfg4r1
- CHCFG4R1
- chcfg4r2
- CHCFG4R2
- chcfg5r1
- CHCFG5R1
- chcfg5r2
- CHCFG5R2
- chcfg6r1
- CHCFG6R1
- chcfg6r2
- CHCFG6R2
- chcfg7r1
- CHCFG7R1
- chcfg7r2
- CHCFG7R2
- chdatin0r
- channel data input register
- chdatin1r
- CHDATIN1R
- chdatin2r
- CHDATIN2R
- chdatin3r
- CHDATIN3R
- chdatin4r
- CHDATIN4R
- chdatin5r
- CHDATIN5R
- chdatin6r
- CHDATIN6R
- chdatin7r
- CHDATIN7R
- chwdat0r
- channel watchdog filter data register
- chwdat1r
- CHWDAT1R
- chwdat2r
- CHWDAT2R
- chwdat3r
- CHWDAT3R
- chwdat4r
- CHWDAT4R
- chwdat5r
- CHWDAT5R
- chwdat6r
- CHWDAT6R
- chwdat7r
- CHWDAT7R
- dfsdm0_
awcfr - analog watchdog clear flag register
- dfsdm0_
awhtr - analog watchdog high threshold register
- dfsdm0_
awltr - analog watchdog low threshold register
- dfsdm0_
awsr - analog watchdog status register
- dfsdm0_
cnvtimr - conversion timer register
- dfsdm0_
cr1 - control register 1
- dfsdm0_
cr2 - control register 2
- dfsdm0_
exmax - Extremes detector maximum register
- dfsdm0_
exmin - Extremes detector minimum register
- dfsdm0_
fcr - filter control register
- dfsdm0_
icr - interrupt flag clear register
- dfsdm0_
isr - interrupt and status register
- dfsdm0_
jchgr - injected channel group selection register
- dfsdm0_
jdatar - data register for injected group
- dfsdm0_
rdatar - data register for the regular channel
- dfsdm1_
awcfr - analog watchdog clear flag register
- dfsdm1_
awhtr - analog watchdog high threshold register
- dfsdm1_
awltr - analog watchdog low threshold register
- dfsdm1_
awsr - analog watchdog status register
- dfsdm1_
cnvtimr - conversion timer register
- dfsdm1_
cr1 - control register 1
- dfsdm1_
cr2 - control register 2
- dfsdm1_
exmax - Extremes detector maximum register
- dfsdm1_
exmin - Extremes detector minimum register
- dfsdm1_
fcr - filter control register
- dfsdm1_
icr - interrupt flag clear register
- dfsdm1_
isr - interrupt and status register
- dfsdm1_
jchgr - injected channel group selection register
- dfsdm1_
jdatar - data register for injected group
- dfsdm1_
rdatar - data register for the regular channel
- dfsdm2_
awcfr - analog watchdog clear flag register
- dfsdm2_
awhtr - analog watchdog high threshold register
- dfsdm2_
awltr - analog watchdog low threshold register
- dfsdm2_
awsr - analog watchdog status register
- dfsdm2_
cnvtimr - conversion timer register
- dfsdm2_
cr1 - control register 1
- dfsdm2_
cr2 - control register 2
- dfsdm2_
exmax - Extremes detector maximum register
- dfsdm2_
exmin - Extremes detector minimum register
- dfsdm2_
fcr - filter control register
- dfsdm2_
icr - interrupt flag clear register
- dfsdm2_
isr - interrupt and status register
- dfsdm2_
jchgr - injected channel group selection register
- dfsdm2_
jdatar - data register for injected group
- dfsdm2_
rdatar - data register for the regular channel
- dfsdm3_
awcfr - analog watchdog clear flag register
- dfsdm3_
awhtr - analog watchdog high threshold register
- dfsdm3_
awltr - analog watchdog low threshold register
- dfsdm3_
awsr - analog watchdog status register
- dfsdm3_
cnvtimr - conversion timer register
- dfsdm3_
cr1 - control register 1
- dfsdm3_
cr2 - control register 2
- dfsdm3_
exmax - Extremes detector maximum register
- dfsdm3_
exmin - Extremes detector minimum register
- dfsdm3_
fcr - filter control register
- dfsdm3_
icr - interrupt flag clear register
- dfsdm3_
isr - interrupt and status register
- dfsdm3_
jchgr - injected channel group selection register
- dfsdm3_
jdatar - data register for injected group
- dfsdm3_
rdatar - data register for the regular channel
Structs§
- AWSCD0R
- analog watchdog and short-circuit detector register
- AWSCD1R
- AWSCD1R
- AWSCD2R
- AWSCD2R
- AWSCD3R
- AWSCD3R
- AWSCD4R
- AWSCD4R
- AWSCD5R
- AWSCD5R
- AWSCD6R
- AWSCD6R
- AWSCD7R
- AWSCD7R
- CHCF
G0R1 - channel configuration y register
- CHCF
G0R2 - channel configuration y register
- CHCF
G1R1 - CHCFG1R1
- CHCF
G1R2 - CHCFG1R2
- CHCF
G2R1 - CHCFG2R1
- CHCF
G2R2 - CHCFG2R2
- CHCF
G3R1 - CHCFG3R1
- CHCF
G3R2 - CHCFG3R2
- CHCF
G4R1 - CHCFG4R1
- CHCF
G4R2 - CHCFG4R2
- CHCF
G5R1 - CHCFG5R1
- CHCF
G5R2 - CHCFG5R2
- CHCF
G6R1 - CHCFG6R1
- CHCF
G6R2 - CHCFG6R2
- CHCF
G7R1 - CHCFG7R1
- CHCF
G7R2 - CHCFG7R2
- CHDATI
N0R - channel data input register
- CHDATI
N1R - CHDATIN1R
- CHDATI
N2R - CHDATIN2R
- CHDATI
N3R - CHDATIN3R
- CHDATI
N4R - CHDATIN4R
- CHDATI
N5R - CHDATIN5R
- CHDATI
N6R - CHDATIN6R
- CHDATI
N7R - CHDATIN7R
- CHWDA
T0R - channel watchdog filter data register
- CHWDA
T1R - CHWDAT1R
- CHWDA
T2R - CHWDAT2R
- CHWDA
T3R - CHWDAT3R
- CHWDA
T4R - CHWDAT4R
- CHWDA
T5R - CHWDAT5R
- CHWDA
T6R - CHWDAT6R
- CHWDA
T7R - CHWDAT7R
- DFSD
M0_ AWCFR - analog watchdog clear flag register
- DFSD
M0_ AWHTR - analog watchdog high threshold register
- DFSD
M0_ AWLTR - analog watchdog low threshold register
- DFSD
M0_ AWSR - analog watchdog status register
- DFSD
M0_ CNVTIMR - conversion timer register
- DFSD
M0_ CR1 - control register 1
- DFSD
M0_ CR2 - control register 2
- DFSD
M0_ EXMAX - Extremes detector maximum register
- DFSD
M0_ EXMIN - Extremes detector minimum register
- DFSD
M0_ FCR - filter control register
- DFSD
M0_ ICR - interrupt flag clear register
- DFSD
M0_ ISR - interrupt and status register
- DFSD
M0_ JCHGR - injected channel group selection register
- DFSD
M0_ JDATAR - data register for injected group
- DFSD
M0_ RDATAR - data register for the regular channel
- DFSD
M1_ AWCFR - analog watchdog clear flag register
- DFSD
M1_ AWHTR - analog watchdog high threshold register
- DFSD
M1_ AWLTR - analog watchdog low threshold register
- DFSD
M1_ AWSR - analog watchdog status register
- DFSD
M1_ CNVTIMR - conversion timer register
- DFSD
M1_ CR1 - control register 1
- DFSD
M1_ CR2 - control register 2
- DFSD
M1_ EXMAX - Extremes detector maximum register
- DFSD
M1_ EXMIN - Extremes detector minimum register
- DFSD
M1_ FCR - filter control register
- DFSD
M1_ ICR - interrupt flag clear register
- DFSD
M1_ ISR - interrupt and status register
- DFSD
M1_ JCHGR - injected channel group selection register
- DFSD
M1_ JDATAR - data register for injected group
- DFSD
M1_ RDATAR - data register for the regular channel
- DFSD
M2_ AWCFR - analog watchdog clear flag register
- DFSD
M2_ AWHTR - analog watchdog high threshold register
- DFSD
M2_ AWLTR - analog watchdog low threshold register
- DFSD
M2_ AWSR - analog watchdog status register
- DFSD
M2_ CNVTIMR - conversion timer register
- DFSD
M2_ CR1 - control register 1
- DFSD
M2_ CR2 - control register 2
- DFSD
M2_ EXMAX - Extremes detector maximum register
- DFSD
M2_ EXMIN - Extremes detector minimum register
- DFSD
M2_ FCR - filter control register
- DFSD
M2_ ICR - interrupt flag clear register
- DFSD
M2_ ISR - interrupt and status register
- DFSD
M2_ JCHGR - injected channel group selection register
- DFSD
M2_ JDATAR - data register for injected group
- DFSD
M2_ RDATAR - data register for the regular channel
- DFSD
M3_ AWCFR - analog watchdog clear flag register
- DFSD
M3_ AWHTR - analog watchdog high threshold register
- DFSD
M3_ AWLTR - analog watchdog low threshold register
- DFSD
M3_ AWSR - analog watchdog status register
- DFSD
M3_ CNVTIMR - conversion timer register
- DFSD
M3_ CR1 - control register 1
- DFSD
M3_ CR2 - control register 2
- DFSD
M3_ EXMAX - Extremes detector maximum register
- DFSD
M3_ EXMIN - Extremes detector minimum register
- DFSD
M3_ FCR - filter control register
- DFSD
M3_ ICR - interrupt flag clear register
- DFSD
M3_ ISR - interrupt and status register
- DFSD
M3_ JCHGR - injected channel group selection register
- DFSD
M3_ JDATAR - data register for injected group
- DFSD
M3_ RDATAR - data register for the regular channel
- Register
Block - Register block