stm32l1xx_hal/
dma.rs

1//! Direct Memory Access Engine
2use crate::rcc::Rcc;
3
4#[derive(Debug)]
5pub enum Error {
6    Overrun,
7    BufferError,
8}
9
10#[derive(Debug)]
11pub enum Event {
12    HalfTransfer,
13    TransferComplete,
14}
15
16pub trait DmaExt {
17    type Channels;
18
19    fn dma(self, rcc: &mut Rcc) -> Self::Channels;
20}
21
22macro_rules! dma {
23    ($($DMAX:ident: ($dmaX:ident, $dmaXen:ident, $dmaXrst:ident, {
24        $($CX:ident: (
25            $ccrX:ident,
26            $CCRX:ident,
27            $cndtrX:ident,
28            $CNDTRX:ident,
29            $cparX:ident,
30            $CPARX:ident,
31            $cmarX:ident,
32            $CMARX:ident,
33            $htifX:ident,
34            $tcifX:ident,
35            $chtifX:ident,
36            $ctcifX:ident,
37            $cgifX:ident
38        ),)+
39    }),)+) => {
40        $(
41            pub mod $dmaX {
42                use crate::stm32::{$DMAX};
43                use crate::dma::{DmaExt, Event};
44                use crate::rcc::Rcc;
45
46                #[derive(Debug)]
47                pub struct Channels((), $(pub $CX),+);
48
49                $(
50                    #[derive(Debug)]
51                    pub struct $CX { _0: () }
52
53                    #[allow(dead_code)]
54                    impl $CX {
55                        pub fn listen(&mut self, event: Event) {
56                            match event {
57                                Event::HalfTransfer => unsafe {
58                                    (*$DMAX::ptr()).$ccrX.modify(|_, w| w.htie().set_bit())
59                                },
60                                Event::TransferComplete => unsafe {
61                                    (*$DMAX::ptr()).$ccrX.modify(|_, w| w.tcie().set_bit())
62                                }
63                            }
64                        }
65
66                        pub fn unlisten(&mut self, event: Event) {
67                            match event {
68                                Event::HalfTransfer => unsafe {
69                                    (*$DMAX::ptr()).$ccrX.modify(|_, w| w.htie().clear_bit())
70                                },
71                                Event::TransferComplete => unsafe {
72                                    (*$DMAX::ptr()).$ccrX.modify(|_, w| w.tcie().clear_bit())
73                                }
74                            }
75                        }
76                    }
77                )+
78
79                impl DmaExt for $DMAX {
80                    type Channels = Channels;
81
82                    fn dma(self, rcc: &mut Rcc) -> Channels {
83                        rcc.rb.ahbenr.modify(|_, w| w.$dmaXen().set_bit());
84                        // reset the DMA control registers (stops all on-going transfers)
85                        $(
86                            self.$ccrX.reset();
87                        )+
88                        Channels((), $($CX { _0: () }),+)
89                    }
90                }
91            }
92        )+
93    }
94}
95
96dma! {
97    DMA1: (dma1, dma1en, dma1rst, {
98        C1: (
99            ccr1, CCR1,
100            cndtr1, CNDTR1,
101            cpar1, CPAR1,
102            cmar1, CMAR1,
103            htif1, tcif1,
104            chtif1, ctcif1, cgif1
105        ),
106        C2: (
107            ccr2, CCR2,
108            cndtr2, CNDTR2,
109            cpar2, CPAR2,
110            cmar2, CMAR2,
111            htif2, tcif2,
112            chtif2, ctcif2, cgif2
113        ),
114        C3: (
115            ccr3, CCR3,
116            cndtr3, CNDTR3,
117            cpar3, CPAR3,
118            cmar3, CMAR3,
119            htif3, tcif3,
120            chtif3, ctcif3, cgif3
121        ),
122        C4: (
123            ccr4, CCR4,
124            cndtr4, CNDTR4,
125            cpar4, CPAR4,
126            cmar4, CMAR4,
127            htif4, tcif4,
128            chtif4, ctcif4, cgif4
129        ),
130        C5: (
131            ccr5, CCR5,
132            cndtr5, CNDTR5,
133            cpar5, CPAR5,
134            cmar5, CMAR5,
135            htif5, tcif5,
136            chtif5, ctcif5, cgif5
137        ),
138        C6: (
139            ccr6, CCR6,
140            cndtr6, CNDTR6,
141            cpar6, CPAR6,
142            cmar6, CMAR6,
143            htif6, tcif6,
144            chtif6, ctcif6, cgif6
145        ),
146        C7: (
147            ccr7, CCR7,
148            cndtr7, CNDTR7,
149            cpar7, CPAR7,
150            cmar7, CMAR7,
151            htif7, tcif7,
152            chtif7, ctcif7, cgif7
153        ),
154    }),
155}
156
157dma! {
158    DMA2: (dma2, dma2en, dma2rst, {
159        C1: (
160            ccr1, CCR1,
161            cndtr1, CNDTR1,
162            cpar1, CPAR1,
163            cmar1, CMAR1,
164            htif1, tcif1,
165            chtif1, ctcif1, cgif1
166        ),
167        C2: (
168            ccr2, CCR2,
169            cndtr2, CNDTR2,
170            cpar2, CPAR2,
171            cmar2, CMAR2,
172            htif2, tcif2,
173            chtif2, ctcif2, cgif2
174        ),
175        C3: (
176            ccr3, CCR3,
177            cndtr3, CNDTR3,
178            cpar3, CPAR3,
179            cmar3, CMAR3,
180            htif3, tcif3,
181            chtif3, ctcif3, cgif3
182        ),
183        C4: (
184            ccr4, CCR4,
185            cndtr4, CNDTR4,
186            cpar4, CPAR4,
187            cmar4, CMAR4,
188            htif4, tcif4,
189            chtif4, ctcif4, cgif4
190        ),
191        C5: (
192            ccr5, CCR5,
193            cndtr5, CNDTR5,
194            cpar5, CPAR5,
195            cmar5, CMAR5,
196            htif5, tcif5,
197            chtif5, ctcif5, cgif5
198        ),
199    }),
200}
stm32l1xx_hal/dma.rs

stm32l1xx_hal/
dma.rs
