stm32l1/stm32l162/rtc/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**Wakeup clock selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum WUCKSEL {
12    ///0: RTC/16 clock is selected
13    Div16 = 0,
14    ///1: RTC/8 clock is selected
15    Div8 = 1,
16    ///2: RTC/4 clock is selected
17    Div4 = 2,
18    ///3: RTC/2 clock is selected
19    Div2 = 3,
20    ///4: ck_spre (usually 1 Hz) clock is selected
21    ClockSpare = 4,
22    ///6: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
23    ClockSpareWithOffset = 6,
24}
25impl From<WUCKSEL> for u8 {
26    #[inline(always)]
27    fn from(variant: WUCKSEL) -> Self {
28        variant as _
29    }
30}
31impl crate::FieldSpec for WUCKSEL {
32    type Ux = u8;
33}
34impl crate::IsEnum for WUCKSEL {}
35///Field `WUCKSEL` reader - Wakeup clock selection
36pub type WUCKSEL_R = crate::FieldReader<WUCKSEL>;
37impl WUCKSEL_R {
38    ///Get enumerated values variant
39    #[inline(always)]
40    pub const fn variant(&self) -> Option<WUCKSEL> {
41        match self.bits {
42            0 => Some(WUCKSEL::Div16),
43            1 => Some(WUCKSEL::Div8),
44            2 => Some(WUCKSEL::Div4),
45            3 => Some(WUCKSEL::Div2),
46            4 => Some(WUCKSEL::ClockSpare),
47            6 => Some(WUCKSEL::ClockSpareWithOffset),
48            _ => None,
49        }
50    }
51    ///RTC/16 clock is selected
52    #[inline(always)]
53    pub fn is_div16(&self) -> bool {
54        *self == WUCKSEL::Div16
55    }
56    ///RTC/8 clock is selected
57    #[inline(always)]
58    pub fn is_div8(&self) -> bool {
59        *self == WUCKSEL::Div8
60    }
61    ///RTC/4 clock is selected
62    #[inline(always)]
63    pub fn is_div4(&self) -> bool {
64        *self == WUCKSEL::Div4
65    }
66    ///RTC/2 clock is selected
67    #[inline(always)]
68    pub fn is_div2(&self) -> bool {
69        *self == WUCKSEL::Div2
70    }
71    ///ck_spre (usually 1 Hz) clock is selected
72    #[inline(always)]
73    pub fn is_clock_spare(&self) -> bool {
74        *self == WUCKSEL::ClockSpare
75    }
76    ///ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
77    #[inline(always)]
78    pub fn is_clock_spare_with_offset(&self) -> bool {
79        *self == WUCKSEL::ClockSpareWithOffset
80    }
81}
82///Field `WUCKSEL` writer - Wakeup clock selection
83pub type WUCKSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, WUCKSEL>;
84impl<'a, REG> WUCKSEL_W<'a, REG>
85where
86    REG: crate::Writable + crate::RegisterSpec,
87    REG::Ux: From<u8>,
88{
89    ///RTC/16 clock is selected
90    #[inline(always)]
91    pub fn div16(self) -> &'a mut crate::W<REG> {
92        self.variant(WUCKSEL::Div16)
93    }
94    ///RTC/8 clock is selected
95    #[inline(always)]
96    pub fn div8(self) -> &'a mut crate::W<REG> {
97        self.variant(WUCKSEL::Div8)
98    }
99    ///RTC/4 clock is selected
100    #[inline(always)]
101    pub fn div4(self) -> &'a mut crate::W<REG> {
102        self.variant(WUCKSEL::Div4)
103    }
104    ///RTC/2 clock is selected
105    #[inline(always)]
106    pub fn div2(self) -> &'a mut crate::W<REG> {
107        self.variant(WUCKSEL::Div2)
108    }
109    ///ck_spre (usually 1 Hz) clock is selected
110    #[inline(always)]
111    pub fn clock_spare(self) -> &'a mut crate::W<REG> {
112        self.variant(WUCKSEL::ClockSpare)
113    }
114    ///ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
115    #[inline(always)]
116    pub fn clock_spare_with_offset(self) -> &'a mut crate::W<REG> {
117        self.variant(WUCKSEL::ClockSpareWithOffset)
118    }
119}
120/**Time-stamp event active edge
121
122Value on reset: 0*/
123#[cfg_attr(feature = "defmt", derive(defmt::Format))]
124#[derive(Clone, Copy, Debug, PartialEq, Eq)]
125pub enum TSEDGE {
126    ///0: RTC_TS input rising edge generates a time-stamp event
127    RisingEdge = 0,
128    ///1: RTC_TS input falling edge generates a time-stamp event
129    FallingEdge = 1,
130}
131impl From<TSEDGE> for bool {
132    #[inline(always)]
133    fn from(variant: TSEDGE) -> Self {
134        variant as u8 != 0
135    }
136}
137///Field `TSEDGE` reader - Time-stamp event active edge
138pub type TSEDGE_R = crate::BitReader<TSEDGE>;
139impl TSEDGE_R {
140    ///Get enumerated values variant
141    #[inline(always)]
142    pub const fn variant(&self) -> TSEDGE {
143        match self.bits {
144            false => TSEDGE::RisingEdge,
145            true => TSEDGE::FallingEdge,
146        }
147    }
148    ///RTC_TS input rising edge generates a time-stamp event
149    #[inline(always)]
150    pub fn is_rising_edge(&self) -> bool {
151        *self == TSEDGE::RisingEdge
152    }
153    ///RTC_TS input falling edge generates a time-stamp event
154    #[inline(always)]
155    pub fn is_falling_edge(&self) -> bool {
156        *self == TSEDGE::FallingEdge
157    }
158}
159///Field `TSEDGE` writer - Time-stamp event active edge
160pub type TSEDGE_W<'a, REG> = crate::BitWriter<'a, REG, TSEDGE>;
161impl<'a, REG> TSEDGE_W<'a, REG>
162where
163    REG: crate::Writable + crate::RegisterSpec,
164{
165    ///RTC_TS input rising edge generates a time-stamp event
166    #[inline(always)]
167    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
168        self.variant(TSEDGE::RisingEdge)
169    }
170    ///RTC_TS input falling edge generates a time-stamp event
171    #[inline(always)]
172    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
173        self.variant(TSEDGE::FallingEdge)
174    }
175}
176/**Reference clock detection enable
177
178Value on reset: 0*/
179#[cfg_attr(feature = "defmt", derive(defmt::Format))]
180#[derive(Clone, Copy, Debug, PartialEq, Eq)]
181pub enum REFCKON {
182    ///0: RTC_REFIN detection disabled
183    Disabled = 0,
184    ///1: RTC_REFIN detection enabled
185    Enabled = 1,
186}
187impl From<REFCKON> for bool {
188    #[inline(always)]
189    fn from(variant: REFCKON) -> Self {
190        variant as u8 != 0
191    }
192}
193///Field `REFCKON` reader - Reference clock detection enable
194pub type REFCKON_R = crate::BitReader<REFCKON>;
195impl REFCKON_R {
196    ///Get enumerated values variant
197    #[inline(always)]
198    pub const fn variant(&self) -> REFCKON {
199        match self.bits {
200            false => REFCKON::Disabled,
201            true => REFCKON::Enabled,
202        }
203    }
204    ///RTC_REFIN detection disabled
205    #[inline(always)]
206    pub fn is_disabled(&self) -> bool {
207        *self == REFCKON::Disabled
208    }
209    ///RTC_REFIN detection enabled
210    #[inline(always)]
211    pub fn is_enabled(&self) -> bool {
212        *self == REFCKON::Enabled
213    }
214}
215///Field `REFCKON` writer - Reference clock detection enable
216pub type REFCKON_W<'a, REG> = crate::BitWriter<'a, REG, REFCKON>;
217impl<'a, REG> REFCKON_W<'a, REG>
218where
219    REG: crate::Writable + crate::RegisterSpec,
220{
221    ///RTC_REFIN detection disabled
222    #[inline(always)]
223    pub fn disabled(self) -> &'a mut crate::W<REG> {
224        self.variant(REFCKON::Disabled)
225    }
226    ///RTC_REFIN detection enabled
227    #[inline(always)]
228    pub fn enabled(self) -> &'a mut crate::W<REG> {
229        self.variant(REFCKON::Enabled)
230    }
231}
232/**Bypass the shadow registers
233
234Value on reset: 0*/
235#[cfg_attr(feature = "defmt", derive(defmt::Format))]
236#[derive(Clone, Copy, Debug, PartialEq, Eq)]
237pub enum BYPSHAD {
238    ///0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
239    ShadowReg = 0,
240    ///1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
241    BypassShadowReg = 1,
242}
243impl From<BYPSHAD> for bool {
244    #[inline(always)]
245    fn from(variant: BYPSHAD) -> Self {
246        variant as u8 != 0
247    }
248}
249///Field `BYPSHAD` reader - Bypass the shadow registers
250pub type BYPSHAD_R = crate::BitReader<BYPSHAD>;
251impl BYPSHAD_R {
252    ///Get enumerated values variant
253    #[inline(always)]
254    pub const fn variant(&self) -> BYPSHAD {
255        match self.bits {
256            false => BYPSHAD::ShadowReg,
257            true => BYPSHAD::BypassShadowReg,
258        }
259    }
260    ///Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
261    #[inline(always)]
262    pub fn is_shadow_reg(&self) -> bool {
263        *self == BYPSHAD::ShadowReg
264    }
265    ///Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
266    #[inline(always)]
267    pub fn is_bypass_shadow_reg(&self) -> bool {
268        *self == BYPSHAD::BypassShadowReg
269    }
270}
271///Field `BYPSHAD` writer - Bypass the shadow registers
272pub type BYPSHAD_W<'a, REG> = crate::BitWriter<'a, REG, BYPSHAD>;
273impl<'a, REG> BYPSHAD_W<'a, REG>
274where
275    REG: crate::Writable + crate::RegisterSpec,
276{
277    ///Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
278    #[inline(always)]
279    pub fn shadow_reg(self) -> &'a mut crate::W<REG> {
280        self.variant(BYPSHAD::ShadowReg)
281    }
282    ///Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
283    #[inline(always)]
284    pub fn bypass_shadow_reg(self) -> &'a mut crate::W<REG> {
285        self.variant(BYPSHAD::BypassShadowReg)
286    }
287}
288/**Hour format
289
290Value on reset: 0*/
291#[cfg_attr(feature = "defmt", derive(defmt::Format))]
292#[derive(Clone, Copy, Debug, PartialEq, Eq)]
293pub enum FMT {
294    ///0: 24 hour/day format
295    TwentyFourHour = 0,
296    ///1: AM/PM hour format
297    AmPm = 1,
298}
299impl From<FMT> for bool {
300    #[inline(always)]
301    fn from(variant: FMT) -> Self {
302        variant as u8 != 0
303    }
304}
305///Field `FMT` reader - Hour format
306pub type FMT_R = crate::BitReader<FMT>;
307impl FMT_R {
308    ///Get enumerated values variant
309    #[inline(always)]
310    pub const fn variant(&self) -> FMT {
311        match self.bits {
312            false => FMT::TwentyFourHour,
313            true => FMT::AmPm,
314        }
315    }
316    ///24 hour/day format
317    #[inline(always)]
318    pub fn is_twenty_four_hour(&self) -> bool {
319        *self == FMT::TwentyFourHour
320    }
321    ///AM/PM hour format
322    #[inline(always)]
323    pub fn is_am_pm(&self) -> bool {
324        *self == FMT::AmPm
325    }
326}
327///Field `FMT` writer - Hour format
328pub type FMT_W<'a, REG> = crate::BitWriter<'a, REG, FMT>;
329impl<'a, REG> FMT_W<'a, REG>
330where
331    REG: crate::Writable + crate::RegisterSpec,
332{
333    ///24 hour/day format
334    #[inline(always)]
335    pub fn twenty_four_hour(self) -> &'a mut crate::W<REG> {
336        self.variant(FMT::TwentyFourHour)
337    }
338    ///AM/PM hour format
339    #[inline(always)]
340    pub fn am_pm(self) -> &'a mut crate::W<REG> {
341        self.variant(FMT::AmPm)
342    }
343}
344///Field `DCE` reader - Coarse digital calibration enable
345pub type DCE_R = crate::BitReader;
346///Field `DCE` writer - Coarse digital calibration enable
347pub type DCE_W<'a, REG> = crate::BitWriter<'a, REG>;
348/**Alarm %s enable
349
350Value on reset: 0*/
351#[cfg_attr(feature = "defmt", derive(defmt::Format))]
352#[derive(Clone, Copy, Debug, PartialEq, Eq)]
353pub enum ALRAE {
354    ///0: Alarm disabled
355    Disabled = 0,
356    ///1: Alarm enabled
357    Enabled = 1,
358}
359impl From<ALRAE> for bool {
360    #[inline(always)]
361    fn from(variant: ALRAE) -> Self {
362        variant as u8 != 0
363    }
364}
365///Field `ALRE(A,B)` reader - Alarm %s enable
366pub type ALRE_R = crate::BitReader<ALRAE>;
367impl ALRE_R {
368    ///Get enumerated values variant
369    #[inline(always)]
370    pub const fn variant(&self) -> ALRAE {
371        match self.bits {
372            false => ALRAE::Disabled,
373            true => ALRAE::Enabled,
374        }
375    }
376    ///Alarm disabled
377    #[inline(always)]
378    pub fn is_disabled(&self) -> bool {
379        *self == ALRAE::Disabled
380    }
381    ///Alarm enabled
382    #[inline(always)]
383    pub fn is_enabled(&self) -> bool {
384        *self == ALRAE::Enabled
385    }
386}
387///Field `ALRE(A,B)` writer - Alarm %s enable
388pub type ALRE_W<'a, REG> = crate::BitWriter<'a, REG, ALRAE>;
389impl<'a, REG> ALRE_W<'a, REG>
390where
391    REG: crate::Writable + crate::RegisterSpec,
392{
393    ///Alarm disabled
394    #[inline(always)]
395    pub fn disabled(self) -> &'a mut crate::W<REG> {
396        self.variant(ALRAE::Disabled)
397    }
398    ///Alarm enabled
399    #[inline(always)]
400    pub fn enabled(self) -> &'a mut crate::W<REG> {
401        self.variant(ALRAE::Enabled)
402    }
403}
404/**Wakeup timer enable
405
406Value on reset: 0*/
407#[cfg_attr(feature = "defmt", derive(defmt::Format))]
408#[derive(Clone, Copy, Debug, PartialEq, Eq)]
409pub enum WUTE {
410    ///0: Wakeup timer disabled
411    Disabled = 0,
412    ///1: Wakeup timer enabled
413    Enabled = 1,
414}
415impl From<WUTE> for bool {
416    #[inline(always)]
417    fn from(variant: WUTE) -> Self {
418        variant as u8 != 0
419    }
420}
421///Field `WUTE` reader - Wakeup timer enable
422pub type WUTE_R = crate::BitReader<WUTE>;
423impl WUTE_R {
424    ///Get enumerated values variant
425    #[inline(always)]
426    pub const fn variant(&self) -> WUTE {
427        match self.bits {
428            false => WUTE::Disabled,
429            true => WUTE::Enabled,
430        }
431    }
432    ///Wakeup timer disabled
433    #[inline(always)]
434    pub fn is_disabled(&self) -> bool {
435        *self == WUTE::Disabled
436    }
437    ///Wakeup timer enabled
438    #[inline(always)]
439    pub fn is_enabled(&self) -> bool {
440        *self == WUTE::Enabled
441    }
442}
443///Field `WUTE` writer - Wakeup timer enable
444pub type WUTE_W<'a, REG> = crate::BitWriter<'a, REG, WUTE>;
445impl<'a, REG> WUTE_W<'a, REG>
446where
447    REG: crate::Writable + crate::RegisterSpec,
448{
449    ///Wakeup timer disabled
450    #[inline(always)]
451    pub fn disabled(self) -> &'a mut crate::W<REG> {
452        self.variant(WUTE::Disabled)
453    }
454    ///Wakeup timer enabled
455    #[inline(always)]
456    pub fn enabled(self) -> &'a mut crate::W<REG> {
457        self.variant(WUTE::Enabled)
458    }
459}
460/**Time stamp enable
461
462Value on reset: 0*/
463#[cfg_attr(feature = "defmt", derive(defmt::Format))]
464#[derive(Clone, Copy, Debug, PartialEq, Eq)]
465pub enum TSE {
466    ///0: Timestamp disabled
467    Disabled = 0,
468    ///1: Timestamp enabled
469    Enabled = 1,
470}
471impl From<TSE> for bool {
472    #[inline(always)]
473    fn from(variant: TSE) -> Self {
474        variant as u8 != 0
475    }
476}
477///Field `TSE` reader - Time stamp enable
478pub type TSE_R = crate::BitReader<TSE>;
479impl TSE_R {
480    ///Get enumerated values variant
481    #[inline(always)]
482    pub const fn variant(&self) -> TSE {
483        match self.bits {
484            false => TSE::Disabled,
485            true => TSE::Enabled,
486        }
487    }
488    ///Timestamp disabled
489    #[inline(always)]
490    pub fn is_disabled(&self) -> bool {
491        *self == TSE::Disabled
492    }
493    ///Timestamp enabled
494    #[inline(always)]
495    pub fn is_enabled(&self) -> bool {
496        *self == TSE::Enabled
497    }
498}
499///Field `TSE` writer - Time stamp enable
500pub type TSE_W<'a, REG> = crate::BitWriter<'a, REG, TSE>;
501impl<'a, REG> TSE_W<'a, REG>
502where
503    REG: crate::Writable + crate::RegisterSpec,
504{
505    ///Timestamp disabled
506    #[inline(always)]
507    pub fn disabled(self) -> &'a mut crate::W<REG> {
508        self.variant(TSE::Disabled)
509    }
510    ///Timestamp enabled
511    #[inline(always)]
512    pub fn enabled(self) -> &'a mut crate::W<REG> {
513        self.variant(TSE::Enabled)
514    }
515}
516/**Alarm %s interrupt enable
517
518Value on reset: 0*/
519#[cfg_attr(feature = "defmt", derive(defmt::Format))]
520#[derive(Clone, Copy, Debug, PartialEq, Eq)]
521pub enum ALRAIE {
522    ///0: Alarm Interrupt disabled
523    Disabled = 0,
524    ///1: Alarm Interrupt enabled
525    Enabled = 1,
526}
527impl From<ALRAIE> for bool {
528    #[inline(always)]
529    fn from(variant: ALRAIE) -> Self {
530        variant as u8 != 0
531    }
532}
533///Field `ALRIE(A,B)` reader - Alarm %s interrupt enable
534pub type ALRIE_R = crate::BitReader<ALRAIE>;
535impl ALRIE_R {
536    ///Get enumerated values variant
537    #[inline(always)]
538    pub const fn variant(&self) -> ALRAIE {
539        match self.bits {
540            false => ALRAIE::Disabled,
541            true => ALRAIE::Enabled,
542        }
543    }
544    ///Alarm Interrupt disabled
545    #[inline(always)]
546    pub fn is_disabled(&self) -> bool {
547        *self == ALRAIE::Disabled
548    }
549    ///Alarm Interrupt enabled
550    #[inline(always)]
551    pub fn is_enabled(&self) -> bool {
552        *self == ALRAIE::Enabled
553    }
554}
555///Field `ALRIE(A,B)` writer - Alarm %s interrupt enable
556pub type ALRIE_W<'a, REG> = crate::BitWriter<'a, REG, ALRAIE>;
557impl<'a, REG> ALRIE_W<'a, REG>
558where
559    REG: crate::Writable + crate::RegisterSpec,
560{
561    ///Alarm Interrupt disabled
562    #[inline(always)]
563    pub fn disabled(self) -> &'a mut crate::W<REG> {
564        self.variant(ALRAIE::Disabled)
565    }
566    ///Alarm Interrupt enabled
567    #[inline(always)]
568    pub fn enabled(self) -> &'a mut crate::W<REG> {
569        self.variant(ALRAIE::Enabled)
570    }
571}
572/**Wakeup timer interrupt enable
573
574Value on reset: 0*/
575#[cfg_attr(feature = "defmt", derive(defmt::Format))]
576#[derive(Clone, Copy, Debug, PartialEq, Eq)]
577pub enum WUTIE {
578    ///0: Wakeup timer interrupt disabled
579    Disabled = 0,
580    ///1: Wakeup timer interrupt enabled
581    Enabled = 1,
582}
583impl From<WUTIE> for bool {
584    #[inline(always)]
585    fn from(variant: WUTIE) -> Self {
586        variant as u8 != 0
587    }
588}
589///Field `WUTIE` reader - Wakeup timer interrupt enable
590pub type WUTIE_R = crate::BitReader<WUTIE>;
591impl WUTIE_R {
592    ///Get enumerated values variant
593    #[inline(always)]
594    pub const fn variant(&self) -> WUTIE {
595        match self.bits {
596            false => WUTIE::Disabled,
597            true => WUTIE::Enabled,
598        }
599    }
600    ///Wakeup timer interrupt disabled
601    #[inline(always)]
602    pub fn is_disabled(&self) -> bool {
603        *self == WUTIE::Disabled
604    }
605    ///Wakeup timer interrupt enabled
606    #[inline(always)]
607    pub fn is_enabled(&self) -> bool {
608        *self == WUTIE::Enabled
609    }
610}
611///Field `WUTIE` writer - Wakeup timer interrupt enable
612pub type WUTIE_W<'a, REG> = crate::BitWriter<'a, REG, WUTIE>;
613impl<'a, REG> WUTIE_W<'a, REG>
614where
615    REG: crate::Writable + crate::RegisterSpec,
616{
617    ///Wakeup timer interrupt disabled
618    #[inline(always)]
619    pub fn disabled(self) -> &'a mut crate::W<REG> {
620        self.variant(WUTIE::Disabled)
621    }
622    ///Wakeup timer interrupt enabled
623    #[inline(always)]
624    pub fn enabled(self) -> &'a mut crate::W<REG> {
625        self.variant(WUTIE::Enabled)
626    }
627}
628/**Time-stamp interrupt enable
629
630Value on reset: 0*/
631#[cfg_attr(feature = "defmt", derive(defmt::Format))]
632#[derive(Clone, Copy, Debug, PartialEq, Eq)]
633pub enum TSIE {
634    ///0: Time-stamp Interrupt disabled
635    Disabled = 0,
636    ///1: Time-stamp Interrupt enabled
637    Enabled = 1,
638}
639impl From<TSIE> for bool {
640    #[inline(always)]
641    fn from(variant: TSIE) -> Self {
642        variant as u8 != 0
643    }
644}
645///Field `TSIE` reader - Time-stamp interrupt enable
646pub type TSIE_R = crate::BitReader<TSIE>;
647impl TSIE_R {
648    ///Get enumerated values variant
649    #[inline(always)]
650    pub const fn variant(&self) -> TSIE {
651        match self.bits {
652            false => TSIE::Disabled,
653            true => TSIE::Enabled,
654        }
655    }
656    ///Time-stamp Interrupt disabled
657    #[inline(always)]
658    pub fn is_disabled(&self) -> bool {
659        *self == TSIE::Disabled
660    }
661    ///Time-stamp Interrupt enabled
662    #[inline(always)]
663    pub fn is_enabled(&self) -> bool {
664        *self == TSIE::Enabled
665    }
666}
667///Field `TSIE` writer - Time-stamp interrupt enable
668pub type TSIE_W<'a, REG> = crate::BitWriter<'a, REG, TSIE>;
669impl<'a, REG> TSIE_W<'a, REG>
670where
671    REG: crate::Writable + crate::RegisterSpec,
672{
673    ///Time-stamp Interrupt disabled
674    #[inline(always)]
675    pub fn disabled(self) -> &'a mut crate::W<REG> {
676        self.variant(TSIE::Disabled)
677    }
678    ///Time-stamp Interrupt enabled
679    #[inline(always)]
680    pub fn enabled(self) -> &'a mut crate::W<REG> {
681        self.variant(TSIE::Enabled)
682    }
683}
684/**Add 1 hour
685
686Value on reset: 0*/
687#[cfg_attr(feature = "defmt", derive(defmt::Format))]
688#[derive(Clone, Copy, Debug, PartialEq, Eq)]
689pub enum ADD1HW {
690    ///1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
691    Add1 = 1,
692}
693impl From<ADD1HW> for bool {
694    #[inline(always)]
695    fn from(variant: ADD1HW) -> Self {
696        variant as u8 != 0
697    }
698}
699///Field `ADD1H` reader - Add 1 hour
700pub type ADD1H_R = crate::BitReader<ADD1HW>;
701impl ADD1H_R {
702    ///Get enumerated values variant
703    #[inline(always)]
704    pub const fn variant(&self) -> Option<ADD1HW> {
705        match self.bits {
706            true => Some(ADD1HW::Add1),
707            _ => None,
708        }
709    }
710    ///Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
711    #[inline(always)]
712    pub fn is_add1(&self) -> bool {
713        *self == ADD1HW::Add1
714    }
715}
716///Field `ADD1H` writer - Add 1 hour
717pub type ADD1H_W<'a, REG> = crate::BitWriter<'a, REG, ADD1HW>;
718impl<'a, REG> ADD1H_W<'a, REG>
719where
720    REG: crate::Writable + crate::RegisterSpec,
721{
722    ///Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
723    #[inline(always)]
724    pub fn add1(self) -> &'a mut crate::W<REG> {
725        self.variant(ADD1HW::Add1)
726    }
727}
728/**Subtract 1 hour
729
730Value on reset: 0*/
731#[cfg_attr(feature = "defmt", derive(defmt::Format))]
732#[derive(Clone, Copy, Debug, PartialEq, Eq)]
733pub enum SUB1HW {
734    ///1: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
735    Sub1 = 1,
736}
737impl From<SUB1HW> for bool {
738    #[inline(always)]
739    fn from(variant: SUB1HW) -> Self {
740        variant as u8 != 0
741    }
742}
743///Field `SUB1H` reader - Subtract 1 hour
744pub type SUB1H_R = crate::BitReader<SUB1HW>;
745impl SUB1H_R {
746    ///Get enumerated values variant
747    #[inline(always)]
748    pub const fn variant(&self) -> Option<SUB1HW> {
749        match self.bits {
750            true => Some(SUB1HW::Sub1),
751            _ => None,
752        }
753    }
754    ///Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
755    #[inline(always)]
756    pub fn is_sub1(&self) -> bool {
757        *self == SUB1HW::Sub1
758    }
759}
760///Field `SUB1H` writer - Subtract 1 hour
761pub type SUB1H_W<'a, REG> = crate::BitWriter<'a, REG, SUB1HW>;
762impl<'a, REG> SUB1H_W<'a, REG>
763where
764    REG: crate::Writable + crate::RegisterSpec,
765{
766    ///Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
767    #[inline(always)]
768    pub fn sub1(self) -> &'a mut crate::W<REG> {
769        self.variant(SUB1HW::Sub1)
770    }
771}
772/**Backup
773
774Value on reset: 0*/
775#[cfg_attr(feature = "defmt", derive(defmt::Format))]
776#[derive(Clone, Copy, Debug, PartialEq, Eq)]
777pub enum BKP {
778    ///0: Daylight Saving Time change has not been performed
779    DstNotChanged = 0,
780    ///1: Daylight Saving Time change has been performed
781    DstChanged = 1,
782}
783impl From<BKP> for bool {
784    #[inline(always)]
785    fn from(variant: BKP) -> Self {
786        variant as u8 != 0
787    }
788}
789///Field `BKP` reader - Backup
790pub type BKP_R = crate::BitReader<BKP>;
791impl BKP_R {
792    ///Get enumerated values variant
793    #[inline(always)]
794    pub const fn variant(&self) -> BKP {
795        match self.bits {
796            false => BKP::DstNotChanged,
797            true => BKP::DstChanged,
798        }
799    }
800    ///Daylight Saving Time change has not been performed
801    #[inline(always)]
802    pub fn is_dst_not_changed(&self) -> bool {
803        *self == BKP::DstNotChanged
804    }
805    ///Daylight Saving Time change has been performed
806    #[inline(always)]
807    pub fn is_dst_changed(&self) -> bool {
808        *self == BKP::DstChanged
809    }
810}
811///Field `BKP` writer - Backup
812pub type BKP_W<'a, REG> = crate::BitWriter<'a, REG, BKP>;
813impl<'a, REG> BKP_W<'a, REG>
814where
815    REG: crate::Writable + crate::RegisterSpec,
816{
817    ///Daylight Saving Time change has not been performed
818    #[inline(always)]
819    pub fn dst_not_changed(self) -> &'a mut crate::W<REG> {
820        self.variant(BKP::DstNotChanged)
821    }
822    ///Daylight Saving Time change has been performed
823    #[inline(always)]
824    pub fn dst_changed(self) -> &'a mut crate::W<REG> {
825        self.variant(BKP::DstChanged)
826    }
827}
828/**Calibration output selection
829
830Value on reset: 0*/
831#[cfg_attr(feature = "defmt", derive(defmt::Format))]
832#[derive(Clone, Copy, Debug, PartialEq, Eq)]
833pub enum COSEL {
834    ///0: Calibration output is 512 Hz (with default prescaler setting)
835    CalFreq512hz = 0,
836    ///1: Calibration output is 1 Hz (with default prescaler setting)
837    CalFreq1hz = 1,
838}
839impl From<COSEL> for bool {
840    #[inline(always)]
841    fn from(variant: COSEL) -> Self {
842        variant as u8 != 0
843    }
844}
845///Field `COSEL` reader - Calibration output selection
846pub type COSEL_R = crate::BitReader<COSEL>;
847impl COSEL_R {
848    ///Get enumerated values variant
849    #[inline(always)]
850    pub const fn variant(&self) -> COSEL {
851        match self.bits {
852            false => COSEL::CalFreq512hz,
853            true => COSEL::CalFreq1hz,
854        }
855    }
856    ///Calibration output is 512 Hz (with default prescaler setting)
857    #[inline(always)]
858    pub fn is_cal_freq_512hz(&self) -> bool {
859        *self == COSEL::CalFreq512hz
860    }
861    ///Calibration output is 1 Hz (with default prescaler setting)
862    #[inline(always)]
863    pub fn is_cal_freq_1hz(&self) -> bool {
864        *self == COSEL::CalFreq1hz
865    }
866}
867///Field `COSEL` writer - Calibration output selection
868pub type COSEL_W<'a, REG> = crate::BitWriter<'a, REG, COSEL>;
869impl<'a, REG> COSEL_W<'a, REG>
870where
871    REG: crate::Writable + crate::RegisterSpec,
872{
873    ///Calibration output is 512 Hz (with default prescaler setting)
874    #[inline(always)]
875    pub fn cal_freq_512hz(self) -> &'a mut crate::W<REG> {
876        self.variant(COSEL::CalFreq512hz)
877    }
878    ///Calibration output is 1 Hz (with default prescaler setting)
879    #[inline(always)]
880    pub fn cal_freq_1hz(self) -> &'a mut crate::W<REG> {
881        self.variant(COSEL::CalFreq1hz)
882    }
883}
884/**Output polarity
885
886Value on reset: 0*/
887#[cfg_attr(feature = "defmt", derive(defmt::Format))]
888#[derive(Clone, Copy, Debug, PartialEq, Eq)]
889pub enum POL {
890    ///0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
891    High = 0,
892    ///1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
893    Low = 1,
894}
895impl From<POL> for bool {
896    #[inline(always)]
897    fn from(variant: POL) -> Self {
898        variant as u8 != 0
899    }
900}
901///Field `POL` reader - Output polarity
902pub type POL_R = crate::BitReader<POL>;
903impl POL_R {
904    ///Get enumerated values variant
905    #[inline(always)]
906    pub const fn variant(&self) -> POL {
907        match self.bits {
908            false => POL::High,
909            true => POL::Low,
910        }
911    }
912    ///The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
913    #[inline(always)]
914    pub fn is_high(&self) -> bool {
915        *self == POL::High
916    }
917    ///The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
918    #[inline(always)]
919    pub fn is_low(&self) -> bool {
920        *self == POL::Low
921    }
922}
923///Field `POL` writer - Output polarity
924pub type POL_W<'a, REG> = crate::BitWriter<'a, REG, POL>;
925impl<'a, REG> POL_W<'a, REG>
926where
927    REG: crate::Writable + crate::RegisterSpec,
928{
929    ///The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
930    #[inline(always)]
931    pub fn high(self) -> &'a mut crate::W<REG> {
932        self.variant(POL::High)
933    }
934    ///The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
935    #[inline(always)]
936    pub fn low(self) -> &'a mut crate::W<REG> {
937        self.variant(POL::Low)
938    }
939}
940/**Output selection
941
942Value on reset: 0*/
943#[cfg_attr(feature = "defmt", derive(defmt::Format))]
944#[derive(Clone, Copy, Debug, PartialEq, Eq)]
945#[repr(u8)]
946pub enum OSEL {
947    ///0: Output disabled
948    Disabled = 0,
949    ///1: Alarm A output enabled
950    AlarmA = 1,
951    ///2: Alarm B output enabled
952    AlarmB = 2,
953    ///3: Wakeup output enabled
954    Wakeup = 3,
955}
956impl From<OSEL> for u8 {
957    #[inline(always)]
958    fn from(variant: OSEL) -> Self {
959        variant as _
960    }
961}
962impl crate::FieldSpec for OSEL {
963    type Ux = u8;
964}
965impl crate::IsEnum for OSEL {}
966///Field `OSEL` reader - Output selection
967pub type OSEL_R = crate::FieldReader<OSEL>;
968impl OSEL_R {
969    ///Get enumerated values variant
970    #[inline(always)]
971    pub const fn variant(&self) -> OSEL {
972        match self.bits {
973            0 => OSEL::Disabled,
974            1 => OSEL::AlarmA,
975            2 => OSEL::AlarmB,
976            3 => OSEL::Wakeup,
977            _ => unreachable!(),
978        }
979    }
980    ///Output disabled
981    #[inline(always)]
982    pub fn is_disabled(&self) -> bool {
983        *self == OSEL::Disabled
984    }
985    ///Alarm A output enabled
986    #[inline(always)]
987    pub fn is_alarm_a(&self) -> bool {
988        *self == OSEL::AlarmA
989    }
990    ///Alarm B output enabled
991    #[inline(always)]
992    pub fn is_alarm_b(&self) -> bool {
993        *self == OSEL::AlarmB
994    }
995    ///Wakeup output enabled
996    #[inline(always)]
997    pub fn is_wakeup(&self) -> bool {
998        *self == OSEL::Wakeup
999    }
1000}
1001///Field `OSEL` writer - Output selection
1002pub type OSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OSEL, crate::Safe>;
1003impl<'a, REG> OSEL_W<'a, REG>
1004where
1005    REG: crate::Writable + crate::RegisterSpec,
1006    REG::Ux: From<u8>,
1007{
1008    ///Output disabled
1009    #[inline(always)]
1010    pub fn disabled(self) -> &'a mut crate::W<REG> {
1011        self.variant(OSEL::Disabled)
1012    }
1013    ///Alarm A output enabled
1014    #[inline(always)]
1015    pub fn alarm_a(self) -> &'a mut crate::W<REG> {
1016        self.variant(OSEL::AlarmA)
1017    }
1018    ///Alarm B output enabled
1019    #[inline(always)]
1020    pub fn alarm_b(self) -> &'a mut crate::W<REG> {
1021        self.variant(OSEL::AlarmB)
1022    }
1023    ///Wakeup output enabled
1024    #[inline(always)]
1025    pub fn wakeup(self) -> &'a mut crate::W<REG> {
1026        self.variant(OSEL::Wakeup)
1027    }
1028}
1029/**Calibration output enable
1030
1031Value on reset: 0*/
1032#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1033#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1034pub enum COE {
1035    ///0: Calibration output disabled
1036    Disabled = 0,
1037    ///1: Calibration output enabled
1038    Enabled = 1,
1039}
1040impl From<COE> for bool {
1041    #[inline(always)]
1042    fn from(variant: COE) -> Self {
1043        variant as u8 != 0
1044    }
1045}
1046///Field `COE` reader - Calibration output enable
1047pub type COE_R = crate::BitReader<COE>;
1048impl COE_R {
1049    ///Get enumerated values variant
1050    #[inline(always)]
1051    pub const fn variant(&self) -> COE {
1052        match self.bits {
1053            false => COE::Disabled,
1054            true => COE::Enabled,
1055        }
1056    }
1057    ///Calibration output disabled
1058    #[inline(always)]
1059    pub fn is_disabled(&self) -> bool {
1060        *self == COE::Disabled
1061    }
1062    ///Calibration output enabled
1063    #[inline(always)]
1064    pub fn is_enabled(&self) -> bool {
1065        *self == COE::Enabled
1066    }
1067}
1068///Field `COE` writer - Calibration output enable
1069pub type COE_W<'a, REG> = crate::BitWriter<'a, REG, COE>;
1070impl<'a, REG> COE_W<'a, REG>
1071where
1072    REG: crate::Writable + crate::RegisterSpec,
1073{
1074    ///Calibration output disabled
1075    #[inline(always)]
1076    pub fn disabled(self) -> &'a mut crate::W<REG> {
1077        self.variant(COE::Disabled)
1078    }
1079    ///Calibration output enabled
1080    #[inline(always)]
1081    pub fn enabled(self) -> &'a mut crate::W<REG> {
1082        self.variant(COE::Enabled)
1083    }
1084}
1085impl R {
1086    ///Bits 0:2 - Wakeup clock selection
1087    #[inline(always)]
1088    pub fn wucksel(&self) -> WUCKSEL_R {
1089        WUCKSEL_R::new((self.bits & 7) as u8)
1090    }
1091    ///Bit 3 - Time-stamp event active edge
1092    #[inline(always)]
1093    pub fn tsedge(&self) -> TSEDGE_R {
1094        TSEDGE_R::new(((self.bits >> 3) & 1) != 0)
1095    }
1096    ///Bit 4 - Reference clock detection enable
1097    #[inline(always)]
1098    pub fn refckon(&self) -> REFCKON_R {
1099        REFCKON_R::new(((self.bits >> 4) & 1) != 0)
1100    }
1101    ///Bit 5 - Bypass the shadow registers
1102    #[inline(always)]
1103    pub fn bypshad(&self) -> BYPSHAD_R {
1104        BYPSHAD_R::new(((self.bits >> 5) & 1) != 0)
1105    }
1106    ///Bit 6 - Hour format
1107    #[inline(always)]
1108    pub fn fmt(&self) -> FMT_R {
1109        FMT_R::new(((self.bits >> 6) & 1) != 0)
1110    }
1111    ///Bit 7 - Coarse digital calibration enable
1112    #[inline(always)]
1113    pub fn dce(&self) -> DCE_R {
1114        DCE_R::new(((self.bits >> 7) & 1) != 0)
1115    }
1116    ///Alarm (A,B) enable
1117    ///
1118    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ALRAE` field.</div>
1119    #[inline(always)]
1120    pub fn alre(&self, n: u8) -> ALRE_R {
1121        #[allow(clippy::no_effect)]
1122        [(); 2][n as usize];
1123        ALRE_R::new(((self.bits >> (n + 8)) & 1) != 0)
1124    }
1125    ///Iterator for array of:
1126    ///Alarm (A,B) enable
1127    #[inline(always)]
1128    pub fn alre_iter(&self) -> impl Iterator<Item = ALRE_R> + '_ {
1129        (0..2).map(move |n| ALRE_R::new(((self.bits >> (n + 8)) & 1) != 0))
1130    }
1131    ///Bit 8 - Alarm A enable
1132    #[inline(always)]
1133    pub fn alrae(&self) -> ALRE_R {
1134        ALRE_R::new(((self.bits >> 8) & 1) != 0)
1135    }
1136    ///Bit 9 - Alarm B enable
1137    #[inline(always)]
1138    pub fn alrbe(&self) -> ALRE_R {
1139        ALRE_R::new(((self.bits >> 9) & 1) != 0)
1140    }
1141    ///Bit 10 - Wakeup timer enable
1142    #[inline(always)]
1143    pub fn wute(&self) -> WUTE_R {
1144        WUTE_R::new(((self.bits >> 10) & 1) != 0)
1145    }
1146    ///Bit 11 - Time stamp enable
1147    #[inline(always)]
1148    pub fn tse(&self) -> TSE_R {
1149        TSE_R::new(((self.bits >> 11) & 1) != 0)
1150    }
1151    ///Alarm (A,B) interrupt enable
1152    ///
1153    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ALRAIE` field.</div>
1154    #[inline(always)]
1155    pub fn alrie(&self, n: u8) -> ALRIE_R {
1156        #[allow(clippy::no_effect)]
1157        [(); 2][n as usize];
1158        ALRIE_R::new(((self.bits >> (n + 12)) & 1) != 0)
1159    }
1160    ///Iterator for array of:
1161    ///Alarm (A,B) interrupt enable
1162    #[inline(always)]
1163    pub fn alrie_iter(&self) -> impl Iterator<Item = ALRIE_R> + '_ {
1164        (0..2).map(move |n| ALRIE_R::new(((self.bits >> (n + 12)) & 1) != 0))
1165    }
1166    ///Bit 12 - Alarm A interrupt enable
1167    #[inline(always)]
1168    pub fn alraie(&self) -> ALRIE_R {
1169        ALRIE_R::new(((self.bits >> 12) & 1) != 0)
1170    }
1171    ///Bit 13 - Alarm B interrupt enable
1172    #[inline(always)]
1173    pub fn alrbie(&self) -> ALRIE_R {
1174        ALRIE_R::new(((self.bits >> 13) & 1) != 0)
1175    }
1176    ///Bit 14 - Wakeup timer interrupt enable
1177    #[inline(always)]
1178    pub fn wutie(&self) -> WUTIE_R {
1179        WUTIE_R::new(((self.bits >> 14) & 1) != 0)
1180    }
1181    ///Bit 15 - Time-stamp interrupt enable
1182    #[inline(always)]
1183    pub fn tsie(&self) -> TSIE_R {
1184        TSIE_R::new(((self.bits >> 15) & 1) != 0)
1185    }
1186    ///Bit 16 - Add 1 hour
1187    #[inline(always)]
1188    pub fn add1h(&self) -> ADD1H_R {
1189        ADD1H_R::new(((self.bits >> 16) & 1) != 0)
1190    }
1191    ///Bit 17 - Subtract 1 hour
1192    #[inline(always)]
1193    pub fn sub1h(&self) -> SUB1H_R {
1194        SUB1H_R::new(((self.bits >> 17) & 1) != 0)
1195    }
1196    ///Bit 18 - Backup
1197    #[inline(always)]
1198    pub fn bkp(&self) -> BKP_R {
1199        BKP_R::new(((self.bits >> 18) & 1) != 0)
1200    }
1201    ///Bit 19 - Calibration output selection
1202    #[inline(always)]
1203    pub fn cosel(&self) -> COSEL_R {
1204        COSEL_R::new(((self.bits >> 19) & 1) != 0)
1205    }
1206    ///Bit 20 - Output polarity
1207    #[inline(always)]
1208    pub fn pol(&self) -> POL_R {
1209        POL_R::new(((self.bits >> 20) & 1) != 0)
1210    }
1211    ///Bits 21:22 - Output selection
1212    #[inline(always)]
1213    pub fn osel(&self) -> OSEL_R {
1214        OSEL_R::new(((self.bits >> 21) & 3) as u8)
1215    }
1216    ///Bit 23 - Calibration output enable
1217    #[inline(always)]
1218    pub fn coe(&self) -> COE_R {
1219        COE_R::new(((self.bits >> 23) & 1) != 0)
1220    }
1221}
1222impl core::fmt::Debug for R {
1223    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1224        f.debug_struct("CR")
1225            .field("coe", &self.coe())
1226            .field("osel", &self.osel())
1227            .field("pol", &self.pol())
1228            .field("cosel", &self.cosel())
1229            .field("bkp", &self.bkp())
1230            .field("sub1h", &self.sub1h())
1231            .field("add1h", &self.add1h())
1232            .field("tsie", &self.tsie())
1233            .field("wutie", &self.wutie())
1234            .field("alraie", &self.alraie())
1235            .field("alrbie", &self.alrbie())
1236            .field("tse", &self.tse())
1237            .field("wute", &self.wute())
1238            .field("alrae", &self.alrae())
1239            .field("alrbe", &self.alrbe())
1240            .field("dce", &self.dce())
1241            .field("fmt", &self.fmt())
1242            .field("bypshad", &self.bypshad())
1243            .field("refckon", &self.refckon())
1244            .field("tsedge", &self.tsedge())
1245            .field("wucksel", &self.wucksel())
1246            .finish()
1247    }
1248}
1249impl W {
1250    ///Bits 0:2 - Wakeup clock selection
1251    #[inline(always)]
1252    pub fn wucksel(&mut self) -> WUCKSEL_W<CRrs> {
1253        WUCKSEL_W::new(self, 0)
1254    }
1255    ///Bit 3 - Time-stamp event active edge
1256    #[inline(always)]
1257    pub fn tsedge(&mut self) -> TSEDGE_W<CRrs> {
1258        TSEDGE_W::new(self, 3)
1259    }
1260    ///Bit 4 - Reference clock detection enable
1261    #[inline(always)]
1262    pub fn refckon(&mut self) -> REFCKON_W<CRrs> {
1263        REFCKON_W::new(self, 4)
1264    }
1265    ///Bit 5 - Bypass the shadow registers
1266    #[inline(always)]
1267    pub fn bypshad(&mut self) -> BYPSHAD_W<CRrs> {
1268        BYPSHAD_W::new(self, 5)
1269    }
1270    ///Bit 6 - Hour format
1271    #[inline(always)]
1272    pub fn fmt(&mut self) -> FMT_W<CRrs> {
1273        FMT_W::new(self, 6)
1274    }
1275    ///Bit 7 - Coarse digital calibration enable
1276    #[inline(always)]
1277    pub fn dce(&mut self) -> DCE_W<CRrs> {
1278        DCE_W::new(self, 7)
1279    }
1280    ///Alarm (A,B) enable
1281    ///
1282    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ALRAE` field.</div>
1283    #[inline(always)]
1284    pub fn alre(&mut self, n: u8) -> ALRE_W<CRrs> {
1285        #[allow(clippy::no_effect)]
1286        [(); 2][n as usize];
1287        ALRE_W::new(self, n + 8)
1288    }
1289    ///Bit 8 - Alarm A enable
1290    #[inline(always)]
1291    pub fn alrae(&mut self) -> ALRE_W<CRrs> {
1292        ALRE_W::new(self, 8)
1293    }
1294    ///Bit 9 - Alarm B enable
1295    #[inline(always)]
1296    pub fn alrbe(&mut self) -> ALRE_W<CRrs> {
1297        ALRE_W::new(self, 9)
1298    }
1299    ///Bit 10 - Wakeup timer enable
1300    #[inline(always)]
1301    pub fn wute(&mut self) -> WUTE_W<CRrs> {
1302        WUTE_W::new(self, 10)
1303    }
1304    ///Bit 11 - Time stamp enable
1305    #[inline(always)]
1306    pub fn tse(&mut self) -> TSE_W<CRrs> {
1307        TSE_W::new(self, 11)
1308    }
1309    ///Alarm (A,B) interrupt enable
1310    ///
1311    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ALRAIE` field.</div>
1312    #[inline(always)]
1313    pub fn alrie(&mut self, n: u8) -> ALRIE_W<CRrs> {
1314        #[allow(clippy::no_effect)]
1315        [(); 2][n as usize];
1316        ALRIE_W::new(self, n + 12)
1317    }
1318    ///Bit 12 - Alarm A interrupt enable
1319    #[inline(always)]
1320    pub fn alraie(&mut self) -> ALRIE_W<CRrs> {
1321        ALRIE_W::new(self, 12)
1322    }
1323    ///Bit 13 - Alarm B interrupt enable
1324    #[inline(always)]
1325    pub fn alrbie(&mut self) -> ALRIE_W<CRrs> {
1326        ALRIE_W::new(self, 13)
1327    }
1328    ///Bit 14 - Wakeup timer interrupt enable
1329    #[inline(always)]
1330    pub fn wutie(&mut self) -> WUTIE_W<CRrs> {
1331        WUTIE_W::new(self, 14)
1332    }
1333    ///Bit 15 - Time-stamp interrupt enable
1334    #[inline(always)]
1335    pub fn tsie(&mut self) -> TSIE_W<CRrs> {
1336        TSIE_W::new(self, 15)
1337    }
1338    ///Bit 16 - Add 1 hour
1339    #[inline(always)]
1340    pub fn add1h(&mut self) -> ADD1H_W<CRrs> {
1341        ADD1H_W::new(self, 16)
1342    }
1343    ///Bit 17 - Subtract 1 hour
1344    #[inline(always)]
1345    pub fn sub1h(&mut self) -> SUB1H_W<CRrs> {
1346        SUB1H_W::new(self, 17)
1347    }
1348    ///Bit 18 - Backup
1349    #[inline(always)]
1350    pub fn bkp(&mut self) -> BKP_W<CRrs> {
1351        BKP_W::new(self, 18)
1352    }
1353    ///Bit 19 - Calibration output selection
1354    #[inline(always)]
1355    pub fn cosel(&mut self) -> COSEL_W<CRrs> {
1356        COSEL_W::new(self, 19)
1357    }
1358    ///Bit 20 - Output polarity
1359    #[inline(always)]
1360    pub fn pol(&mut self) -> POL_W<CRrs> {
1361        POL_W::new(self, 20)
1362    }
1363    ///Bits 21:22 - Output selection
1364    #[inline(always)]
1365    pub fn osel(&mut self) -> OSEL_W<CRrs> {
1366        OSEL_W::new(self, 21)
1367    }
1368    ///Bit 23 - Calibration output enable
1369    #[inline(always)]
1370    pub fn coe(&mut self) -> COE_W<CRrs> {
1371        COE_W::new(self, 23)
1372    }
1373}
1374/**control register
1375
1376You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1377
1378See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L162.html#RTC:CR)*/
1379pub struct CRrs;
1380impl crate::RegisterSpec for CRrs {
1381    type Ux = u32;
1382}
1383///`read()` method returns [`cr::R`](R) reader structure
1384impl crate::Readable for CRrs {}
1385///`write(|w| ..)` method takes [`cr::W`](W) writer structure
1386impl crate::Writable for CRrs {
1387    type Safety = crate::Unsafe;
1388}
1389///`reset()` method sets CR to value 0
1390impl crate::Resettable for CRrs {}
stm32l1/stm32l162/rtc/cr.rs

stm32l1/stm32l162/rtc/
cr.rs
