stm32l1/stm32l100/syscfg/
exticr2.rs

1///Register `EXTICR2` reader
2pub type R = crate::R<EXTICR2rs>;
3///Register `EXTICR2` writer
4pub type W = crate::W<EXTICR2rs>;
5///Field `EXTI4` reader - EXTI x configuration (x = 4 to 7)
6pub type EXTI4_R = crate::FieldReader;
7///Field `EXTI4` writer - EXTI x configuration (x = 4 to 7)
8pub type EXTI4_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9///Field `EXTI5` reader - EXTI x configuration (x = 4 to 7)
10pub type EXTI5_R = crate::FieldReader;
11///Field `EXTI5` writer - EXTI x configuration (x = 4 to 7)
12pub type EXTI5_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13///Field `EXTI6` reader - EXTI x configuration (x = 4 to 7)
14pub type EXTI6_R = crate::FieldReader;
15///Field `EXTI6` writer - EXTI x configuration (x = 4 to 7)
16pub type EXTI6_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
17///Field `EXTI7` reader - EXTI x configuration (x = 4 to 7)
18pub type EXTI7_R = crate::FieldReader;
19///Field `EXTI7` writer - EXTI x configuration (x = 4 to 7)
20pub type EXTI7_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21impl R {
22    ///Bits 0:3 - EXTI x configuration (x = 4 to 7)
23    #[inline(always)]
24    pub fn exti4(&self) -> EXTI4_R {
25        EXTI4_R::new((self.bits & 0x0f) as u8)
26    }
27    ///Bits 4:7 - EXTI x configuration (x = 4 to 7)
28    #[inline(always)]
29    pub fn exti5(&self) -> EXTI5_R {
30        EXTI5_R::new(((self.bits >> 4) & 0x0f) as u8)
31    }
32    ///Bits 8:11 - EXTI x configuration (x = 4 to 7)
33    #[inline(always)]
34    pub fn exti6(&self) -> EXTI6_R {
35        EXTI6_R::new(((self.bits >> 8) & 0x0f) as u8)
36    }
37    ///Bits 12:15 - EXTI x configuration (x = 4 to 7)
38    #[inline(always)]
39    pub fn exti7(&self) -> EXTI7_R {
40        EXTI7_R::new(((self.bits >> 12) & 0x0f) as u8)
41    }
42}
43impl core::fmt::Debug for R {
44    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
45        f.debug_struct("EXTICR2")
46            .field("exti7", &self.exti7())
47            .field("exti6", &self.exti6())
48            .field("exti5", &self.exti5())
49            .field("exti4", &self.exti4())
50            .finish()
51    }
52}
53impl W {
54    ///Bits 0:3 - EXTI x configuration (x = 4 to 7)
55    #[inline(always)]
56    pub fn exti4(&mut self) -> EXTI4_W<EXTICR2rs> {
57        EXTI4_W::new(self, 0)
58    }
59    ///Bits 4:7 - EXTI x configuration (x = 4 to 7)
60    #[inline(always)]
61    pub fn exti5(&mut self) -> EXTI5_W<EXTICR2rs> {
62        EXTI5_W::new(self, 4)
63    }
64    ///Bits 8:11 - EXTI x configuration (x = 4 to 7)
65    #[inline(always)]
66    pub fn exti6(&mut self) -> EXTI6_W<EXTICR2rs> {
67        EXTI6_W::new(self, 8)
68    }
69    ///Bits 12:15 - EXTI x configuration (x = 4 to 7)
70    #[inline(always)]
71    pub fn exti7(&mut self) -> EXTI7_W<EXTICR2rs> {
72        EXTI7_W::new(self, 12)
73    }
74}
75/**external interrupt configuration register 2
76
77You can [`read`](crate::Reg::read) this register and get [`exticr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`exticr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
78
79See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L100.html#SYSCFG:EXTICR2)*/
80pub struct EXTICR2rs;
81impl crate::RegisterSpec for EXTICR2rs {
82    type Ux = u32;
83}
84///`read()` method returns [`exticr2::R`](R) reader structure
85impl crate::Readable for EXTICR2rs {}
86///`write(|w| ..)` method takes [`exticr2::W`](W) writer structure
87impl crate::Writable for EXTICR2rs {
88    type Safety = crate::Unsafe;
89}
90///`reset()` method sets EXTICR2 to value 0
91impl crate::Resettable for EXTICR2rs {}
stm32l1/stm32l100/syscfg/exticr2.rs

stm32l1/stm32l100/syscfg/
exticr2.rs
