stm32l1/stm32l162/tim9/
egr.rs

1///Register `EGR` reader
2pub type R = crate::R<EGRrs>;
3///Register `EGR` writer
4pub type W = crate::W<EGRrs>;
5/**Update generation
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum UG {
11    ///1: Re-initializes the timer counter and generates an update of the registers.
12    Update = 1,
13}
14impl From<UG> for bool {
15    #[inline(always)]
16    fn from(variant: UG) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `UG` reader - Update generation
21pub type UG_R = crate::BitReader<UG>;
22impl UG_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> Option<UG> {
26        match self.bits {
27            true => Some(UG::Update),
28            _ => None,
29        }
30    }
31    ///Re-initializes the timer counter and generates an update of the registers.
32    #[inline(always)]
33    pub fn is_update(&self) -> bool {
34        *self == UG::Update
35    }
36}
37///Field `UG` writer - Update generation
38pub type UG_W<'a, REG> = crate::BitWriter<'a, REG, UG>;
39impl<'a, REG> UG_W<'a, REG>
40where
41    REG: crate::Writable + crate::RegisterSpec,
42{
43    ///Re-initializes the timer counter and generates an update of the registers.
44    #[inline(always)]
45    pub fn update(self) -> &'a mut crate::W<REG> {
46        self.variant(UG::Update)
47    }
48}
49/**Capture/compare %s generation
50
51Value on reset: 0*/
52#[cfg_attr(feature = "defmt", derive(defmt::Format))]
53#[derive(Clone, Copy, Debug, PartialEq, Eq)]
54pub enum CC1GW {
55    ///1: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
56    Trigger = 1,
57}
58impl From<CC1GW> for bool {
59    #[inline(always)]
60    fn from(variant: CC1GW) -> Self {
61        variant as u8 != 0
62    }
63}
64///Field `CCG(1-2)` reader - Capture/compare %s generation
65pub type CCG_R = crate::BitReader<CC1GW>;
66impl CCG_R {
67    ///Get enumerated values variant
68    #[inline(always)]
69    pub const fn variant(&self) -> Option<CC1GW> {
70        match self.bits {
71            true => Some(CC1GW::Trigger),
72            _ => None,
73        }
74    }
75    ///If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
76    #[inline(always)]
77    pub fn is_trigger(&self) -> bool {
78        *self == CC1GW::Trigger
79    }
80}
81///Field `CCG(1-2)` writer - Capture/compare %s generation
82pub type CCG_W<'a, REG> = crate::BitWriter<'a, REG, CC1GW>;
83impl<'a, REG> CCG_W<'a, REG>
84where
85    REG: crate::Writable + crate::RegisterSpec,
86{
87    ///If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
88    #[inline(always)]
89    pub fn trigger(self) -> &'a mut crate::W<REG> {
90        self.variant(CC1GW::Trigger)
91    }
92}
93/**Trigger generation
94
95Value on reset: 0*/
96#[cfg_attr(feature = "defmt", derive(defmt::Format))]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98pub enum TGW {
99    ///1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
100    Trigger = 1,
101}
102impl From<TGW> for bool {
103    #[inline(always)]
104    fn from(variant: TGW) -> Self {
105        variant as u8 != 0
106    }
107}
108///Field `TG` reader - Trigger generation
109pub type TG_R = crate::BitReader<TGW>;
110impl TG_R {
111    ///Get enumerated values variant
112    #[inline(always)]
113    pub const fn variant(&self) -> Option<TGW> {
114        match self.bits {
115            true => Some(TGW::Trigger),
116            _ => None,
117        }
118    }
119    ///The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
120    #[inline(always)]
121    pub fn is_trigger(&self) -> bool {
122        *self == TGW::Trigger
123    }
124}
125///Field `TG` writer - Trigger generation
126pub type TG_W<'a, REG> = crate::BitWriter<'a, REG, TGW>;
127impl<'a, REG> TG_W<'a, REG>
128where
129    REG: crate::Writable + crate::RegisterSpec,
130{
131    ///The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
132    #[inline(always)]
133    pub fn trigger(self) -> &'a mut crate::W<REG> {
134        self.variant(TGW::Trigger)
135    }
136}
137impl R {
138    ///Bit 0 - Update generation
139    #[inline(always)]
140    pub fn ug(&self) -> UG_R {
141        UG_R::new((self.bits & 1) != 0)
142    }
143    ///Capture/compare (1-2) generation
144    ///
145    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1G` field.</div>
146    #[inline(always)]
147    pub fn ccg(&self, n: u8) -> CCG_R {
148        #[allow(clippy::no_effect)]
149        [(); 2][n as usize];
150        CCG_R::new(((self.bits >> (n + 1)) & 1) != 0)
151    }
152    ///Iterator for array of:
153    ///Capture/compare (1-2) generation
154    #[inline(always)]
155    pub fn ccg_iter(&self) -> impl Iterator<Item = CCG_R> + '_ {
156        (0..2).map(move |n| CCG_R::new(((self.bits >> (n + 1)) & 1) != 0))
157    }
158    ///Bit 1 - Capture/compare 1 generation
159    #[inline(always)]
160    pub fn cc1g(&self) -> CCG_R {
161        CCG_R::new(((self.bits >> 1) & 1) != 0)
162    }
163    ///Bit 2 - Capture/compare 2 generation
164    #[inline(always)]
165    pub fn cc2g(&self) -> CCG_R {
166        CCG_R::new(((self.bits >> 2) & 1) != 0)
167    }
168    ///Bit 6 - Trigger generation
169    #[inline(always)]
170    pub fn tg(&self) -> TG_R {
171        TG_R::new(((self.bits >> 6) & 1) != 0)
172    }
173}
174impl core::fmt::Debug for R {
175    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
176        f.debug_struct("EGR")
177            .field("tg", &self.tg())
178            .field("cc1g", &self.cc1g())
179            .field("cc2g", &self.cc2g())
180            .field("ug", &self.ug())
181            .finish()
182    }
183}
184impl W {
185    ///Bit 0 - Update generation
186    #[inline(always)]
187    pub fn ug(&mut self) -> UG_W<EGRrs> {
188        UG_W::new(self, 0)
189    }
190    ///Capture/compare (1-2) generation
191    ///
192    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1G` field.</div>
193    #[inline(always)]
194    pub fn ccg(&mut self, n: u8) -> CCG_W<EGRrs> {
195        #[allow(clippy::no_effect)]
196        [(); 2][n as usize];
197        CCG_W::new(self, n + 1)
198    }
199    ///Bit 1 - Capture/compare 1 generation
200    #[inline(always)]
201    pub fn cc1g(&mut self) -> CCG_W<EGRrs> {
202        CCG_W::new(self, 1)
203    }
204    ///Bit 2 - Capture/compare 2 generation
205    #[inline(always)]
206    pub fn cc2g(&mut self) -> CCG_W<EGRrs> {
207        CCG_W::new(self, 2)
208    }
209    ///Bit 6 - Trigger generation
210    #[inline(always)]
211    pub fn tg(&mut self) -> TG_W<EGRrs> {
212        TG_W::new(self, 6)
213    }
214}
215/**event generation register
216
217You can [`read`](crate::Reg::read) this register and get [`egr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
218
219See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L162.html#TIM9:EGR)*/
220pub struct EGRrs;
221impl crate::RegisterSpec for EGRrs {
222    type Ux = u32;
223}
224///`read()` method returns [`egr::R`](R) reader structure
225impl crate::Readable for EGRrs {}
226///`write(|w| ..)` method takes [`egr::W`](W) writer structure
227impl crate::Writable for EGRrs {
228    type Safety = crate::Unsafe;
229}
230///`reset()` method sets EGR to value 0
231impl crate::Resettable for EGRrs {}
stm32l1/stm32l162/tim9/egr.rs

stm32l1/stm32l162/tim9/
egr.rs
