Struct stm32l0xx_hal::stm32::rcc::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub cr: Reg<u32, _CR>,
    pub icscr: Reg<u32, _ICSCR>,
    pub crrcr: Reg<u32, _CRRCR>,
    pub cfgr: Reg<u32, _CFGR>,
    pub cier: Reg<u32, _CIER>,
    pub cifr: Reg<u32, _CIFR>,
    pub cicr: Reg<u32, _CICR>,
    pub ioprstr: Reg<u32, _IOPRSTR>,
    pub ahbrstr: Reg<u32, _AHBRSTR>,
    pub apb2rstr: Reg<u32, _APB2RSTR>,
    pub apb1rstr: Reg<u32, _APB1RSTR>,
    pub iopenr: Reg<u32, _IOPENR>,
    pub ahbenr: Reg<u32, _AHBENR>,
    pub apb2enr: Reg<u32, _APB2ENR>,
    pub apb1enr: Reg<u32, _APB1ENR>,
    pub iopsmen: Reg<u32, _IOPSMEN>,
    pub ahbsmenr: Reg<u32, _AHBSMENR>,
    pub apb2smenr: Reg<u32, _APB2SMENR>,
    pub apb1smenr: Reg<u32, _APB1SMENR>,
    pub ccipr: Reg<u32, _CCIPR>,
    pub csr: Reg<u32, _CSR>,
}

Register block

Fields

cr: Reg<u32, _CR>

0x00 - Clock control register

icscr: Reg<u32, _ICSCR>

0x04 - Internal clock sources calibration register

crrcr: Reg<u32, _CRRCR>

0x08 - Clock recovery RC register

cfgr: Reg<u32, _CFGR>

0x0c - Clock configuration register

cier: Reg<u32, _CIER>

0x10 - Clock interrupt enable register

cifr: Reg<u32, _CIFR>

0x14 - Clock interrupt flag register

cicr: Reg<u32, _CICR>

0x18 - Clock interrupt clear register

ioprstr: Reg<u32, _IOPRSTR>

0x1c - GPIO reset register

ahbrstr: Reg<u32, _AHBRSTR>

0x20 - AHB peripheral reset register

apb2rstr: Reg<u32, _APB2RSTR>

0x24 - APB2 peripheral reset register

apb1rstr: Reg<u32, _APB1RSTR>

0x28 - APB1 peripheral reset register

iopenr: Reg<u32, _IOPENR>

0x2c - GPIO clock enable register

ahbenr: Reg<u32, _AHBENR>

0x30 - AHB peripheral clock enable register

apb2enr: Reg<u32, _APB2ENR>

0x34 - APB2 peripheral clock enable register

apb1enr: Reg<u32, _APB1ENR>

0x38 - APB1 peripheral clock enable register

iopsmen: Reg<u32, _IOPSMEN>

0x3c - GPIO clock enable in sleep mode register

ahbsmenr: Reg<u32, _AHBSMENR>

0x40 - AHB peripheral clock enable in sleep mode register

apb2smenr: Reg<u32, _APB2SMENR>

0x44 - APB2 peripheral clock enable in sleep mode register

apb1smenr: Reg<u32, _APB1SMENR>

0x48 - APB1 peripheral clock enable in sleep mode register

ccipr: Reg<u32, _CCIPR>

0x4c - Clock configuration register

csr: Reg<u32, _CSR>

0x50 - Control and status register