stm32l0/stm32l0x2/tim2/
or.rs

1///Register `OR` reader
2pub type R = crate::R<ORrs>;
3///Register `OR` writer
4pub type W = crate::W<ORrs>;
5/**Timer2 ETR remap
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum ETR_RMP {
12    ///3: TIM2 ETR input is connected to HSI16 when HSI16OUTEN bit is set
13    Hsi = 3,
14    ///5: TIM2 ETR input is connected to LSE
15    Lse = 5,
16    ///6: TIM2 ETR input is connected to COMP2_OUT
17    Comp2Out = 6,
18    ///7: TIM2 ETR input is connected to COMP1_OUT
19    Comp1Out = 7,
20}
21impl From<ETR_RMP> for u8 {
22    #[inline(always)]
23    fn from(variant: ETR_RMP) -> Self {
24        variant as _
25    }
26}
27impl crate::FieldSpec for ETR_RMP {
28    type Ux = u8;
29}
30impl crate::IsEnum for ETR_RMP {}
31///Field `ETR_RMP` reader - Timer2 ETR remap
32pub type ETR_RMP_R = crate::FieldReader<ETR_RMP>;
33impl ETR_RMP_R {
34    ///Get enumerated values variant
35    #[inline(always)]
36    pub const fn variant(&self) -> Option<ETR_RMP> {
37        match self.bits {
38            3 => Some(ETR_RMP::Hsi),
39            5 => Some(ETR_RMP::Lse),
40            6 => Some(ETR_RMP::Comp2Out),
41            7 => Some(ETR_RMP::Comp1Out),
42            _ => None,
43        }
44    }
45    ///TIM2 ETR input is connected to HSI16 when HSI16OUTEN bit is set
46    #[inline(always)]
47    pub fn is_hsi(&self) -> bool {
48        *self == ETR_RMP::Hsi
49    }
50    ///TIM2 ETR input is connected to LSE
51    #[inline(always)]
52    pub fn is_lse(&self) -> bool {
53        *self == ETR_RMP::Lse
54    }
55    ///TIM2 ETR input is connected to COMP2_OUT
56    #[inline(always)]
57    pub fn is_comp2_out(&self) -> bool {
58        *self == ETR_RMP::Comp2Out
59    }
60    ///TIM2 ETR input is connected to COMP1_OUT
61    #[inline(always)]
62    pub fn is_comp1_out(&self) -> bool {
63        *self == ETR_RMP::Comp1Out
64    }
65}
66///Field `ETR_RMP` writer - Timer2 ETR remap
67pub type ETR_RMP_W<'a, REG> = crate::FieldWriter<'a, REG, 3, ETR_RMP>;
68impl<'a, REG> ETR_RMP_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    ///TIM2 ETR input is connected to HSI16 when HSI16OUTEN bit is set
74    #[inline(always)]
75    pub fn hsi(self) -> &'a mut crate::W<REG> {
76        self.variant(ETR_RMP::Hsi)
77    }
78    ///TIM2 ETR input is connected to LSE
79    #[inline(always)]
80    pub fn lse(self) -> &'a mut crate::W<REG> {
81        self.variant(ETR_RMP::Lse)
82    }
83    ///TIM2 ETR input is connected to COMP2_OUT
84    #[inline(always)]
85    pub fn comp2_out(self) -> &'a mut crate::W<REG> {
86        self.variant(ETR_RMP::Comp2Out)
87    }
88    ///TIM2 ETR input is connected to COMP1_OUT
89    #[inline(always)]
90    pub fn comp1_out(self) -> &'a mut crate::W<REG> {
91        self.variant(ETR_RMP::Comp1Out)
92    }
93}
94/**Internal trigger
95
96Value on reset: 0*/
97#[cfg_attr(feature = "defmt", derive(defmt::Format))]
98#[derive(Clone, Copy, Debug, PartialEq, Eq)]
99#[repr(u8)]
100pub enum TI4_RMP {
101    ///1: TIM2 TI4 input connected to COMP2_OUT
102    Comp2Out = 1,
103    ///2: TIM2 TI4 input connected to COMP1_OUT
104    Comp1Out = 2,
105}
106impl From<TI4_RMP> for u8 {
107    #[inline(always)]
108    fn from(variant: TI4_RMP) -> Self {
109        variant as _
110    }
111}
112impl crate::FieldSpec for TI4_RMP {
113    type Ux = u8;
114}
115impl crate::IsEnum for TI4_RMP {}
116///Field `TI4_RMP` reader - Internal trigger
117pub type TI4_RMP_R = crate::FieldReader<TI4_RMP>;
118impl TI4_RMP_R {
119    ///Get enumerated values variant
120    #[inline(always)]
121    pub const fn variant(&self) -> Option<TI4_RMP> {
122        match self.bits {
123            1 => Some(TI4_RMP::Comp2Out),
124            2 => Some(TI4_RMP::Comp1Out),
125            _ => None,
126        }
127    }
128    ///TIM2 TI4 input connected to COMP2_OUT
129    #[inline(always)]
130    pub fn is_comp2_out(&self) -> bool {
131        *self == TI4_RMP::Comp2Out
132    }
133    ///TIM2 TI4 input connected to COMP1_OUT
134    #[inline(always)]
135    pub fn is_comp1_out(&self) -> bool {
136        *self == TI4_RMP::Comp1Out
137    }
138}
139///Field `TI4_RMP` writer - Internal trigger
140pub type TI4_RMP_W<'a, REG> = crate::FieldWriter<'a, REG, 2, TI4_RMP>;
141impl<'a, REG> TI4_RMP_W<'a, REG>
142where
143    REG: crate::Writable + crate::RegisterSpec,
144    REG::Ux: From<u8>,
145{
146    ///TIM2 TI4 input connected to COMP2_OUT
147    #[inline(always)]
148    pub fn comp2_out(self) -> &'a mut crate::W<REG> {
149        self.variant(TI4_RMP::Comp2Out)
150    }
151    ///TIM2 TI4 input connected to COMP1_OUT
152    #[inline(always)]
153    pub fn comp1_out(self) -> &'a mut crate::W<REG> {
154        self.variant(TI4_RMP::Comp1Out)
155    }
156}
157impl R {
158    ///Bits 0:2 - Timer2 ETR remap
159    #[inline(always)]
160    pub fn etr_rmp(&self) -> ETR_RMP_R {
161        ETR_RMP_R::new((self.bits & 7) as u8)
162    }
163    ///Bits 3:4 - Internal trigger
164    #[inline(always)]
165    pub fn ti4_rmp(&self) -> TI4_RMP_R {
166        TI4_RMP_R::new(((self.bits >> 3) & 3) as u8)
167    }
168}
169impl core::fmt::Debug for R {
170    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
171        f.debug_struct("OR")
172            .field("etr_rmp", &self.etr_rmp())
173            .field("ti4_rmp", &self.ti4_rmp())
174            .finish()
175    }
176}
177impl W {
178    ///Bits 0:2 - Timer2 ETR remap
179    #[inline(always)]
180    pub fn etr_rmp(&mut self) -> ETR_RMP_W<ORrs> {
181        ETR_RMP_W::new(self, 0)
182    }
183    ///Bits 3:4 - Internal trigger
184    #[inline(always)]
185    pub fn ti4_rmp(&mut self) -> TI4_RMP_W<ORrs> {
186        TI4_RMP_W::new(self, 3)
187    }
188}
189/**TIM2 option register
190
191You can [`read`](crate::Reg::read) this register and get [`or::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`or::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
192
193See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x2.html#TIM2:OR)*/
194pub struct ORrs;
195impl crate::RegisterSpec for ORrs {
196    type Ux = u32;
197}
198///`read()` method returns [`or::R`](R) reader structure
199impl crate::Readable for ORrs {}
200///`write(|w| ..)` method takes [`or::W`](W) writer structure
201impl crate::Writable for ORrs {
202    type Safety = crate::Unsafe;
203}
204///`reset()` method sets OR to value 0
205impl crate::Resettable for ORrs {}
stm32l0/stm32l0x2/tim2/or.rs

stm32l0/stm32l0x2/tim2/
or.rs
