stm32l0/stm32l0x0/
mod.rs

1/*!Peripheral access API for STM32L0X0 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 2;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU};
16#[cfg(feature = "rt")]
17pub use cortex_m_rt::interrupt;
18#[cfg(feature = "rt")]
19extern "C" {
20    fn WWDG();
21    fn RTC();
22    fn FLASH();
23    fn RCC();
24    fn EXTI0_1();
25    fn EXTI2_3();
26    fn EXTI4_15();
27    fn DMA1_CHANNEL1();
28    fn DMA1_CHANNEL2_3();
29    fn DMA1_CHANNEL4_7();
30    fn ADC();
31    fn LPTIM1();
32    fn TIM2();
33    fn TIM21();
34    fn TIM22();
35    fn I2C1();
36    fn SPI1();
37    fn USART2();
38    fn LPUART1();
39}
40#[doc(hidden)]
41#[repr(C)]
42pub union Vector {
43    _handler: unsafe extern "C" fn(),
44    _reserved: u32,
45}
46#[cfg(feature = "rt")]
47#[doc(hidden)]
48#[link_section = ".vector_table.interrupts"]
49#[no_mangle]
50pub static __INTERRUPTS: [Vector; 30] = [
51    Vector { _handler: WWDG },
52    Vector { _reserved: 0 },
53    Vector { _handler: RTC },
54    Vector { _handler: FLASH },
55    Vector { _handler: RCC },
56    Vector { _handler: EXTI0_1 },
57    Vector { _handler: EXTI2_3 },
58    Vector { _handler: EXTI4_15 },
59    Vector { _reserved: 0 },
60    Vector {
61        _handler: DMA1_CHANNEL1,
62    },
63    Vector {
64        _handler: DMA1_CHANNEL2_3,
65    },
66    Vector {
67        _handler: DMA1_CHANNEL4_7,
68    },
69    Vector { _handler: ADC },
70    Vector { _handler: LPTIM1 },
71    Vector { _reserved: 0 },
72    Vector { _handler: TIM2 },
73    Vector { _reserved: 0 },
74    Vector { _reserved: 0 },
75    Vector { _reserved: 0 },
76    Vector { _reserved: 0 },
77    Vector { _handler: TIM21 },
78    Vector { _reserved: 0 },
79    Vector { _handler: TIM22 },
80    Vector { _handler: I2C1 },
81    Vector { _reserved: 0 },
82    Vector { _handler: SPI1 },
83    Vector { _reserved: 0 },
84    Vector { _reserved: 0 },
85    Vector { _handler: USART2 },
86    Vector { _handler: LPUART1 },
87];
88///Enumeration of all the interrupts.
89#[cfg_attr(feature = "defmt", derive(defmt::Format))]
90#[derive(Copy, Clone, Debug, PartialEq, Eq)]
91#[repr(u16)]
92pub enum Interrupt {
93    ///0 - Window Watchdog interrupt
94    WWDG = 0,
95    ///2 - RTC global interrupt
96    RTC = 2,
97    ///3 - Flash global interrupt
98    FLASH = 3,
99    ///4 - RCC global interrupt
100    RCC = 4,
101    ///5 - EXTI Line\[1:0\] interrupts
102    EXTI0_1 = 5,
103    ///6 - EXTI Line\[3:2\] interrupts
104    EXTI2_3 = 6,
105    ///7 - EXTI Line15 and EXTI4 interrupts
106    EXTI4_15 = 7,
107    ///9 - DMA1 Channel1 global interrupt
108    DMA1_CHANNEL1 = 9,
109    ///10 - DMA1 Channel2 and 3 interrupts
110    DMA1_CHANNEL2_3 = 10,
111    ///11 - DMA1 Channel4 to 7 interrupts
112    DMA1_CHANNEL4_7 = 11,
113    ///12 - ADC
114    ADC = 12,
115    ///13 - LPTIMER1 interrupt through EXTI29
116    LPTIM1 = 13,
117    ///15 - TIM2 global interrupt
118    TIM2 = 15,
119    ///20 - TIMER21 global interrupt
120    TIM21 = 20,
121    ///22 - TIMER22 global interrupt
122    TIM22 = 22,
123    ///23 - I2C1 global interrupt
124    I2C1 = 23,
125    ///25 - SPI1_global_interrupt
126    SPI1 = 25,
127    ///28 - USART2 global interrupt
128    USART2 = 28,
129    ///29 - LPUART1 global interrupt through
130    LPUART1 = 29,
131}
132unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
133    #[inline(always)]
134    fn number(self) -> u16 {
135        self as u16
136    }
137}
138///Direct memory access controller
139///
140///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#DMA1)
141pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
142impl core::fmt::Debug for DMA1 {
143    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
144        f.debug_struct("DMA1").finish()
145    }
146}
147///Direct memory access controller
148pub mod dma1;
149///Cyclic redundancy check calculation unit
150///
151///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#CRC)
152pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
153impl core::fmt::Debug for CRC {
154    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
155        f.debug_struct("CRC").finish()
156    }
157}
158///Cyclic redundancy check calculation unit
159pub mod crc;
160///General-purpose I/Os
161///
162///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#GPIOA)
163pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x5000_0000>;
164impl core::fmt::Debug for GPIOA {
165    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
166        f.debug_struct("GPIOA").finish()
167    }
168}
169///General-purpose I/Os
170pub mod gpioa;
171///General-purpose I/Os
172///
173///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#GPIOB)
174pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x5000_0400>;
175impl core::fmt::Debug for GPIOB {
176    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
177        f.debug_struct("GPIOB").finish()
178    }
179}
180///General-purpose I/Os
181pub mod gpiob;
182///General-purpose I/Os
183///
184///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#GPIOB)
185pub type GPIOC = crate::Periph<gpiob::RegisterBlock, 0x5000_0800>;
186impl core::fmt::Debug for GPIOC {
187    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
188        f.debug_struct("GPIOC").finish()
189    }
190}
191///General-purpose I/Os
192pub use self::gpiob as gpioc;
193///General-purpose I/Os
194///
195///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#GPIOB)
196pub type GPIOD = crate::Periph<gpiob::RegisterBlock, 0x5000_0c00>;
197impl core::fmt::Debug for GPIOD {
198    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
199        f.debug_struct("GPIOD").finish()
200    }
201}
202///General-purpose I/Os
203pub use self::gpiob as gpiod;
204///General-purpose I/Os
205///
206///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#GPIOB)
207pub type GPIOH = crate::Periph<gpiob::RegisterBlock, 0x5000_1c00>;
208impl core::fmt::Debug for GPIOH {
209    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
210        f.debug_struct("GPIOH").finish()
211    }
212}
213///General-purpose I/Os
214pub use self::gpiob as gpioh;
215///General-purpose I/Os
216///
217///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#GPIOB)
218pub type GPIOE = crate::Periph<gpiob::RegisterBlock, 0x5000_1000>;
219impl core::fmt::Debug for GPIOE {
220    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
221        f.debug_struct("GPIOE").finish()
222    }
223}
224///General-purpose I/Os
225pub use self::gpiob as gpioe;
226///Low power timer
227///
228///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#LPTIM)
229pub type LPTIM = crate::Periph<lptim::RegisterBlock, 0x4000_7c00>;
230impl core::fmt::Debug for LPTIM {
231    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
232        f.debug_struct("LPTIM").finish()
233    }
234}
235///Low power timer
236pub mod lptim;
237///Real-time clock
238///
239///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#RTC)
240pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
241impl core::fmt::Debug for RTC {
242    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
243        f.debug_struct("RTC").finish()
244    }
245}
246///Real-time clock
247pub mod rtc;
248///Universal synchronous asynchronous receiver transmitter
249///
250///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#USART2)
251pub type USART2 = crate::Periph<usart2::RegisterBlock, 0x4000_4400>;
252impl core::fmt::Debug for USART2 {
253    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
254        f.debug_struct("USART2").finish()
255    }
256}
257///Universal synchronous asynchronous receiver transmitter
258pub mod usart2;
259///Independent watchdog
260///
261///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#IWDG)
262pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
263impl core::fmt::Debug for IWDG {
264    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
265        f.debug_struct("IWDG").finish()
266    }
267}
268///Independent watchdog
269pub mod iwdg;
270///System window watchdog
271///
272///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#WWDG)
273pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
274impl core::fmt::Debug for WWDG {
275    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
276        f.debug_struct("WWDG").finish()
277    }
278}
279///System window watchdog
280pub mod wwdg;
281///Firewall
282///
283///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#FW)
284pub type FW = crate::Periph<fw::RegisterBlock, 0x4001_1c00>;
285impl core::fmt::Debug for FW {
286    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
287        f.debug_struct("FW").finish()
288    }
289}
290///Firewall
291pub mod fw;
292///Reset and clock control
293///
294///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#RCC)
295pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
296impl core::fmt::Debug for RCC {
297    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
298        f.debug_struct("RCC").finish()
299    }
300}
301///Reset and clock control
302pub mod rcc;
303///System configuration controller register
304///
305///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#SYSCFG)
306pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_0000>;
307impl core::fmt::Debug for SYSCFG {
308    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
309        f.debug_struct("SYSCFG").finish()
310    }
311}
312///System configuration controller register
313pub mod syscfg;
314///Serial peripheral interface
315///
316///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#SPI1)
317pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
318impl core::fmt::Debug for SPI1 {
319    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
320        f.debug_struct("SPI1").finish()
321    }
322}
323///Serial peripheral interface
324pub mod spi1;
325///Inter-integrated circuit
326///
327///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#I2C1)
328pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
329impl core::fmt::Debug for I2C1 {
330    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
331        f.debug_struct("I2C1").finish()
332    }
333}
334///Inter-integrated circuit
335pub mod i2c1;
336///Power control
337///
338///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#PWR)
339pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
340impl core::fmt::Debug for PWR {
341    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
342        f.debug_struct("PWR").finish()
343    }
344}
345///Power control
346pub mod pwr;
347///Flash
348///
349///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#FLASH)
350pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
351impl core::fmt::Debug for FLASH {
352    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
353        f.debug_struct("FLASH").finish()
354    }
355}
356///Flash
357pub mod flash;
358///External interrupt/event controller
359///
360///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#EXTI)
361pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
362impl core::fmt::Debug for EXTI {
363    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
364        f.debug_struct("EXTI").finish()
365    }
366}
367///External interrupt/event controller
368pub mod exti;
369///Analog-to-digital converter
370///
371///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#ADC)
372pub type ADC = crate::Periph<adc::RegisterBlock, 0x4001_2400>;
373impl core::fmt::Debug for ADC {
374    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
375        f.debug_struct("ADC").finish()
376    }
377}
378///Analog-to-digital converter
379pub mod adc;
380///Debug support
381///
382///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#DBG)
383pub type DBG = crate::Periph<dbg::RegisterBlock, 0x4001_5800>;
384impl core::fmt::Debug for DBG {
385    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
386        f.debug_struct("DBG").finish()
387    }
388}
389///Debug support
390pub mod dbg;
391///General-purpose-timers
392///
393///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#TIM2)
394pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
395impl core::fmt::Debug for TIM2 {
396    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
397        f.debug_struct("TIM2").finish()
398    }
399}
400///General-purpose-timers
401pub mod tim2;
402///General-purpose-timers
403///
404///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#TIM21)
405pub type TIM21 = crate::Periph<tim21::RegisterBlock, 0x4001_0800>;
406impl core::fmt::Debug for TIM21 {
407    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
408        f.debug_struct("TIM21").finish()
409    }
410}
411///General-purpose-timers
412pub mod tim21;
413///General-purpose-timers
414///
415///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#TIM22)
416pub type TIM22 = crate::Periph<tim22::RegisterBlock, 0x4001_1400>;
417impl core::fmt::Debug for TIM22 {
418    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
419        f.debug_struct("TIM22").finish()
420    }
421}
422///General-purpose-timers
423pub mod tim22;
424///Lower power Universal asynchronous receiver transmitter
425///
426///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x0.html#LPUART1)
427pub type LPUART1 = crate::Periph<lpuart1::RegisterBlock, 0x4000_4800>;
428impl core::fmt::Debug for LPUART1 {
429    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
430        f.debug_struct("LPUART1").finish()
431    }
432}
433///Lower power Universal asynchronous receiver transmitter
434pub mod lpuart1;
435#[no_mangle]
436static mut DEVICE_PERIPHERALS: bool = false;
437/// All the peripherals.
438#[allow(non_snake_case)]
439pub struct Peripherals {
440    ///DMA1
441    pub DMA1: DMA1,
442    ///CRC
443    pub CRC: CRC,
444    ///GPIOA
445    pub GPIOA: GPIOA,
446    ///GPIOB
447    pub GPIOB: GPIOB,
448    ///GPIOC
449    pub GPIOC: GPIOC,
450    ///GPIOD
451    pub GPIOD: GPIOD,
452    ///GPIOH
453    pub GPIOH: GPIOH,
454    ///GPIOE
455    pub GPIOE: GPIOE,
456    ///LPTIM
457    pub LPTIM: LPTIM,
458    ///RTC
459    pub RTC: RTC,
460    ///USART2
461    pub USART2: USART2,
462    ///IWDG
463    pub IWDG: IWDG,
464    ///WWDG
465    pub WWDG: WWDG,
466    ///FW
467    pub FW: FW,
468    ///RCC
469    pub RCC: RCC,
470    ///SYSCFG
471    pub SYSCFG: SYSCFG,
472    ///SPI1
473    pub SPI1: SPI1,
474    ///I2C1
475    pub I2C1: I2C1,
476    ///PWR
477    pub PWR: PWR,
478    ///FLASH
479    pub FLASH: FLASH,
480    ///EXTI
481    pub EXTI: EXTI,
482    ///ADC
483    pub ADC: ADC,
484    ///DBG
485    pub DBG: DBG,
486    ///TIM2
487    pub TIM2: TIM2,
488    ///TIM21
489    pub TIM21: TIM21,
490    ///TIM22
491    pub TIM22: TIM22,
492    ///LPUART1
493    pub LPUART1: LPUART1,
494}
495impl Peripherals {
496    /// Returns all the peripherals *once*.
497    #[cfg(feature = "critical-section")]
498    #[inline]
499    pub fn take() -> Option<Self> {
500        critical_section::with(|_| {
501            if unsafe { DEVICE_PERIPHERALS } {
502                return None;
503            }
504            Some(unsafe { Peripherals::steal() })
505        })
506    }
507    /// Unchecked version of `Peripherals::take`.
508    ///
509    /// # Safety
510    ///
511    /// Each of the returned peripherals must be used at most once.
512    #[inline]
513    pub unsafe fn steal() -> Self {
514        DEVICE_PERIPHERALS = true;
515        Peripherals {
516            DMA1: DMA1::steal(),
517            CRC: CRC::steal(),
518            GPIOA: GPIOA::steal(),
519            GPIOB: GPIOB::steal(),
520            GPIOC: GPIOC::steal(),
521            GPIOD: GPIOD::steal(),
522            GPIOH: GPIOH::steal(),
523            GPIOE: GPIOE::steal(),
524            LPTIM: LPTIM::steal(),
525            RTC: RTC::steal(),
526            USART2: USART2::steal(),
527            IWDG: IWDG::steal(),
528            WWDG: WWDG::steal(),
529            FW: FW::steal(),
530            RCC: RCC::steal(),
531            SYSCFG: SYSCFG::steal(),
532            SPI1: SPI1::steal(),
533            I2C1: I2C1::steal(),
534            PWR: PWR::steal(),
535            FLASH: FLASH::steal(),
536            EXTI: EXTI::steal(),
537            ADC: ADC::steal(),
538            DBG: DBG::steal(),
539            TIM2: TIM2::steal(),
540            TIM21: TIM21::steal(),
541            TIM22: TIM22::steal(),
542            LPUART1: LPUART1::steal(),
543        }
544    }
545}
stm32l0/stm32l0x0/mod.rs

stm32l0/stm32l0x0/
mod.rs
