stm32l0/stm32l0x1/
dma1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    isr: ISR,
6    ifcr: IFCR,
7    ch: [CH; 7],
8    _reserved3: [u8; 0x14],
9    cselr: CSELR,
10}
11impl RegisterBlock {
12    ///0x00 - interrupt status register
13    #[inline(always)]
14    pub const fn isr(&self) -> &ISR {
15        &self.isr
16    }
17    ///0x04 - interrupt flag clear register
18    #[inline(always)]
19    pub const fn ifcr(&self) -> &IFCR {
20        &self.ifcr
21    }
22    ///0x08..0x94 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
23    ///
24    ///<div class="warning">`n` is the index of cluster in the array. `n == 0` corresponds to `CH1` cluster.</div>
25    #[inline(always)]
26    pub const fn ch(&self, n: usize) -> &CH {
27        &self.ch[n]
28    }
29    ///Iterator for array of:
30    ///0x08..0x94 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
31    #[inline(always)]
32    pub fn ch_iter(&self) -> impl Iterator<Item = &CH> {
33        self.ch.iter()
34    }
35    ///0x08..0x1c - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
36    #[inline(always)]
37    pub const fn ch1(&self) -> &CH {
38        self.ch(0)
39    }
40    ///0x1c..0x30 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
41    #[inline(always)]
42    pub const fn ch2(&self) -> &CH {
43        self.ch(1)
44    }
45    ///0x30..0x44 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
46    #[inline(always)]
47    pub const fn ch3(&self) -> &CH {
48        self.ch(2)
49    }
50    ///0x44..0x58 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
51    #[inline(always)]
52    pub const fn ch4(&self) -> &CH {
53        self.ch(3)
54    }
55    ///0x58..0x6c - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
56    #[inline(always)]
57    pub const fn ch5(&self) -> &CH {
58        self.ch(4)
59    }
60    ///0x6c..0x80 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
61    #[inline(always)]
62    pub const fn ch6(&self) -> &CH {
63        self.ch(5)
64    }
65    ///0x80..0x94 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
66    #[inline(always)]
67    pub const fn ch7(&self) -> &CH {
68        self.ch(6)
69    }
70    ///0xa8 - channel selection register
71    #[inline(always)]
72    pub const fn cselr(&self) -> &CSELR {
73        &self.cselr
74    }
75}
76/**ISR (r) register accessor: interrupt status register
77
78You can [`read`](crate::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
79
80See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x1.html#DMA1:ISR)
81
82For information about available fields see [`mod@isr`] module*/
83pub type ISR = crate::Reg<isr::ISRrs>;
84///interrupt status register
85pub mod isr;
86/**IFCR (w) register accessor: interrupt flag clear register
87
88You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ifcr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
89
90See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x1.html#DMA1:IFCR)
91
92For information about available fields see [`mod@ifcr`] module*/
93pub type IFCR = crate::Reg<ifcr::IFCRrs>;
94///interrupt flag clear register
95pub mod ifcr;
96///Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
97pub use self::ch::CH;
98///Cluster
99///Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
100pub mod ch;
101/**CSELR (rw) register accessor: channel selection register
102
103You can [`read`](crate::Reg::read) this register and get [`cselr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cselr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
104
105See register [structure](https://stm32-rs.github.io/stm32-rs/STM32L0x1.html#DMA1:CSELR)
106
107For information about available fields see [`mod@cselr`] module*/
108pub type CSELR = crate::Reg<cselr::CSELRrs>;
109///channel selection register
110pub mod cselr;
stm32l0/stm32l0x1/dma1.rs

stm32l0/stm32l0x1/
dma1.rs
