Module stm32h7xx_hal::stm32::sdmmc1::dtimer [−][src]
The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.
Structs
DATATIME_W | Write proxy for field |
Type Definitions
DATATIME_R | Reader of field |
R | Reader of register DTIMER |
W | Writer for register DTIMER |