Struct stm32h7xx_hal::stm32::hrtim_timc::RegisterBlock[−][src]

#[repr(C)]pub struct RegisterBlock {
    pub timccr: Reg<u32, _TIMCCR>,
    pub timcisr: Reg<u32, _TIMCISR>,
    pub timcicr: Reg<u32, _TIMCICR>,
    pub timcdier5: Reg<u32, _TIMCDIER5>,
    pub cntcr: Reg<u32, _CNTCR>,
    pub percr: Reg<u32, _PERCR>,
    pub repcr: Reg<u32, _REPCR>,
    pub cmp1cr: Reg<u32, _CMP1CR>,
    pub cmp1ccr: Reg<u32, _CMP1CCR>,
    pub cmp2cr: Reg<u32, _CMP2CR>,
    pub cmp3cr: Reg<u32, _CMP3CR>,
    pub cmp4cr: Reg<u32, _CMP4CR>,
    pub cpt1cr: Reg<u32, _CPT1CR>,
    pub cpt2cr: Reg<u32, _CPT2CR>,
    pub dtcr: Reg<u32, _DTCR>,
    pub setc1r: Reg<u32, _SETC1R>,
    pub rstc1r: Reg<u32, _RSTC1R>,
    pub setc2r: Reg<u32, _SETC2R>,
    pub rstc2r: Reg<u32, _RSTC2R>,
    pub eefcr1: Reg<u32, _EEFCR1>,
    pub eefcr2: Reg<u32, _EEFCR2>,
    pub rstcr: Reg<u32, _RSTCR>,
    pub chpcr: Reg<u32, _CHPCR>,
    pub cpt1ccr: Reg<u32, _CPT1CCR>,
    pub cpt2ccr: Reg<u32, _CPT2CCR>,
    pub outcr: Reg<u32, _OUTCR>,
    pub fltcr: Reg<u32, _FLTCR>,
}

Register block

Fields

timccr: Reg<u32, _TIMCCR>

0x00 - Timerx Control Register

timcisr: Reg<u32, _TIMCISR>

0x04 - Timerx Interrupt Status Register

timcicr: Reg<u32, _TIMCICR>

0x08 - Timerx Interrupt Clear Register

timcdier5: Reg<u32, _TIMCDIER5>

0x0c - TIMxDIER5

cntcr: Reg<u32, _CNTCR>

0x10 - Timerx Counter Register

percr: Reg<u32, _PERCR>

0x14 - Timerx Period Register

repcr: Reg<u32, _REPCR>

0x18 - Timerx Repetition Register

cmp1cr: Reg<u32, _CMP1CR>

0x1c - Timerx Compare 1 Register

cmp1ccr: Reg<u32, _CMP1CCR>

0x20 - Timerx Compare 1 Compound Register

cmp2cr: Reg<u32, _CMP2CR>

0x24 - Timerx Compare 2 Register

cmp3cr: Reg<u32, _CMP3CR>

0x28 - Timerx Compare 3 Register

cmp4cr: Reg<u32, _CMP4CR>

0x2c - Timerx Compare 4 Register

cpt1cr: Reg<u32, _CPT1CR>

0x30 - Timerx Capture 1 Register

cpt2cr: Reg<u32, _CPT2CR>

0x34 - Timerx Capture 2 Register

dtcr: Reg<u32, _DTCR>

0x38 - Timerx Deadtime Register

setc1r: Reg<u32, _SETC1R>

0x3c - Timerx Output1 Set Register

rstc1r: Reg<u32, _RSTC1R>

0x40 - Timerx Output1 Reset Register

setc2r: Reg<u32, _SETC2R>

0x44 - Timerx Output2 Set Register

rstc2r: Reg<u32, _RSTC2R>

0x48 - Timerx Output2 Reset Register

eefcr1: Reg<u32, _EEFCR1>

0x4c - Timerx External Event Filtering Register 1

eefcr2: Reg<u32, _EEFCR2>

0x50 - Timerx External Event Filtering Register 2

rstcr: Reg<u32, _RSTCR>

0x54 - TimerA Reset Register

chpcr: Reg<u32, _CHPCR>

0x58 - Timerx Chopper Register

cpt1ccr: Reg<u32, _CPT1CCR>

0x5c - Timerx Capture 2 Control Register

cpt2ccr: Reg<u32, _CPT2CCR>

0x60 - CPT2xCR

outcr: Reg<u32, _OUTCR>

0x64 - Timerx Output Register

fltcr: Reg<u32, _FLTCR>

0x68 - Timerx Fault Register

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