Struct stm32h7xx_hal::stm32::hrtim_timc::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 27 fields
    pub timccr: Reg<TIMCCR_SPEC>,
    pub timcisr: Reg<TIMCISR_SPEC>,
    pub timcicr: Reg<TIMCICR_SPEC>,
    pub timcdier5: Reg<TIMCDIER5_SPEC>,
    pub cntcr: Reg<CNTCR_SPEC>,
    pub percr: Reg<PERCR_SPEC>,
    pub repcr: Reg<REPCR_SPEC>,
    pub cmp1cr: Reg<CMP1CR_SPEC>,
    pub cmp1ccr: Reg<CMP1CCR_SPEC>,
    pub cmp2cr: Reg<CMP2CR_SPEC>,
    pub cmp3cr: Reg<CMP3CR_SPEC>,
    pub cmp4cr: Reg<CMP4CR_SPEC>,
    pub cpt1cr: Reg<CPT1CR_SPEC>,
    pub cpt2cr: Reg<CPT2CR_SPEC>,
    pub dtcr: Reg<DTCR_SPEC>,
    pub setc1r: Reg<SETC1R_SPEC>,
    pub rstc1r: Reg<RSTC1R_SPEC>,
    pub setc2r: Reg<SETC2R_SPEC>,
    pub rstc2r: Reg<RSTC2R_SPEC>,
    pub eefcr1: Reg<EEFCR1_SPEC>,
    pub eefcr2: Reg<EEFCR2_SPEC>,
    pub rstcr: Reg<RSTCR_SPEC>,
    pub chpcr: Reg<CHPCR_SPEC>,
    pub cpt1ccr: Reg<CPT1CCR_SPEC>,
    pub cpt2ccr: Reg<CPT2CCR_SPEC>,
    pub outcr: Reg<OUTCR_SPEC>,
    pub fltcr: Reg<FLTCR_SPEC>,

}
Expand description

Register block

Fields§

§timccr: Reg<TIMCCR_SPEC>

0x00 - Timerx Control Register

§timcisr: Reg<TIMCISR_SPEC>

0x04 - Timerx Interrupt Status Register

§timcicr: Reg<TIMCICR_SPEC>

0x08 - Timerx Interrupt Clear Register

§timcdier5: Reg<TIMCDIER5_SPEC>

0x0c - TIMxDIER5

§cntcr: Reg<CNTCR_SPEC>

0x10 - Timerx Counter Register

§percr: Reg<PERCR_SPEC>

0x14 - Timerx Period Register

§repcr: Reg<REPCR_SPEC>

0x18 - Timerx Repetition Register

§cmp1cr: Reg<CMP1CR_SPEC>

0x1c - Timerx Compare 1 Register

§cmp1ccr: Reg<CMP1CCR_SPEC>

0x20 - Timerx Compare 1 Compound Register

§cmp2cr: Reg<CMP2CR_SPEC>

0x24 - Timerx Compare 2 Register

§cmp3cr: Reg<CMP3CR_SPEC>

0x28 - Timerx Compare 3 Register

§cmp4cr: Reg<CMP4CR_SPEC>

0x2c - Timerx Compare 4 Register

§cpt1cr: Reg<CPT1CR_SPEC>

0x30 - Timerx Capture 1 Register

§cpt2cr: Reg<CPT2CR_SPEC>

0x34 - Timerx Capture 2 Register

§dtcr: Reg<DTCR_SPEC>

0x38 - Timerx Deadtime Register

§setc1r: Reg<SETC1R_SPEC>

0x3c - Timerx Output1 Set Register

§rstc1r: Reg<RSTC1R_SPEC>

0x40 - Timerx Output1 Reset Register

§setc2r: Reg<SETC2R_SPEC>

0x44 - Timerx Output2 Set Register

§rstc2r: Reg<RSTC2R_SPEC>

0x48 - Timerx Output2 Reset Register

§eefcr1: Reg<EEFCR1_SPEC>

0x4c - Timerx External Event Filtering Register 1

§eefcr2: Reg<EEFCR2_SPEC>

0x50 - Timerx External Event Filtering Register 2

§rstcr: Reg<RSTCR_SPEC>

0x54 - TimerA Reset Register

§chpcr: Reg<CHPCR_SPEC>

0x58 - Timerx Chopper Register

§cpt1ccr: Reg<CPT1CCR_SPEC>

0x5c - Timerx Capture 2 Control Register

§cpt2ccr: Reg<CPT2CCR_SPEC>

0x60 - CPT2xCR

§outcr: Reg<OUTCR_SPEC>

0x64 - Timerx Output Register

§fltcr: Reg<FLTCR_SPEC>

0x68 - Timerx Fault Register

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