Struct stm32h7x3::mdma::mdma_c5isr::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

fn bits(&self) -> u32

Value of the register as raw bits

fn teif5(&self) -> TEIF5R

Bit 0 - Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.

fn ctcif5(&self) -> CTCIF5R

Bit 1 - Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.

fn brtif5(&self) -> BRTIF5R

Bit 2 - Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.

fn btif5(&self) -> BTIF5R

Bit 3 - Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.

fn tcif5(&self) -> TCIF5R

Bit 4 - channel x buffer transfer complete

fn crqa5(&self) -> CRQA5R

Bit 16 - channel x request active flag