Struct stm32h7x3::iwdg::iwdg_pr::R
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[src]
pub struct R { /* fields omitted */ }Value read from the register
Methods
impl R[src]
fn bits(&self) -> u32[src]
Value of the register as raw bits
fn pr(&self) -> PRR[src]
Bits 0:2 - Prescaler divider These bits are write access protected see Section23.3.6: Register access protection. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG_SR register is reset.