Struct stm32h743::rcc::RegisterBlock [−] [src]

#[repr(C)]

pub struct RegisterBlock {
    pub cr: CR,
    pub icscr: ICSCR,
    pub crrcr: CRRCR,
    pub cfgr: CFGR,
    pub d1cfgr: D1CFGR,
    pub d2cfgr: D2CFGR,
    pub d3cfgr: D3CFGR,
    pub pllckselr: PLLCKSELR,
    pub pllcfgr: PLLCFGR,
    pub pll1divr: PLL1DIVR,
    pub pll1fracr: PLL1FRACR,
    pub pll2divr: PLL2DIVR,
    pub pll2fracr: PLL2FRACR,
    pub pll3divr: PLL3DIVR,
    pub pll3fracr: PLL3FRACR,
    pub d1ccipr: D1CCIPR,
    pub d2ccip1r: D2CCIP1R,
    pub d2ccip2r: D2CCIP2R,
    pub d3ccipr: D3CCIPR,
    pub cier: CIER,
    pub cifr: CIFR,
    pub cicr: CICR,
    pub bdcr: BDCR,
    pub csr: CSR,
    pub ahb3rstr: AHB3RSTR,
    pub ahb1rstr: AHB1RSTR,
    pub ahb2rstr: AHB2RSTR,
    pub ahb4rstr: AHB4RSTR,
    pub apb3rstr: APB3RSTR,
    pub apb1lrstr: APB1LRSTR,
    pub apb1hrstr: APB1HRSTR,
    pub apb2rstr: APB2RSTR,
    pub apb4rstr: APB4RSTR,
    pub gcr: GCR,
    pub d3amr: D3AMR,
    pub rsr: RSR,
    pub ahb3enr: AHB3ENR,
    pub ahb1enr: AHB1ENR,
    pub ahb2enr: AHB2ENR,
    pub ahb4enr: AHB4ENR,
    pub apb3enr: APB3ENR,
    pub apb1lenr: APB1LENR,
    pub apb1henr: APB1HENR,
    pub apb2enr: APB2ENR,
    pub apb4enr: APB4ENR,
    pub ahb3lpenr: AHB3LPENR,
    pub ahb1lpenr: AHB1LPENR,
    pub ahb2lpenr: AHB2LPENR,
    pub ahb4lpenr: AHB4LPENR,
    pub apb3lpenr: APB3LPENR,
    pub apb1llpenr: APB1LLPENR,
    pub apb1hlpenr: APB1HLPENR,
    pub apb2lpenr: APB2LPENR,
    pub apb4lpenr: APB4LPENR,
    pub c1_rsr: C1_RSR,
    pub c1_ahb3enr: C1_AHB3ENR,
    pub c1_ahb1enr: C1_AHB1ENR,
    pub c1_ahb2enr: C1_AHB2ENR,
    pub c1_ahb4enr: C1_AHB4ENR,
    pub c1_apb3enr: C1_APB3ENR,
    pub c1_apb1lenr: C1_APB1LENR,
    pub c1_apb1henr: C1_APB1HENR,
    pub c1_apb2enr: C1_APB2ENR,
    pub c1_apb4enr: C1_APB4ENR,
    pub c1_ahb3lpenr: C1_AHB3LPENR,
    pub c1_ahb1lpenr: C1_AHB1LPENR,
    pub c1_ahb2lpenr: C1_AHB2LPENR,
    pub c1_ahb4lpenr: C1_AHB4LPENR,
    pub c1_apb3lpenr: C1_APB3LPENR,
    pub c1_apb1llpenr: C1_APB1LLPENR,
    pub c1_apb1hlpenr: C1_APB1HLPENR,
    pub c1_apb2lpenr: C1_APB2LPENR,
    pub c1_apb4lpenr: C1_APB4LPENR,
    // some fields omitted
}

Register block

Fields

0x00 - clock control register

0x04 - RCC Internal Clock Source Calibration Register

0x08 - RCC Clock Recovery RC Register

0x10 - RCC Clock Configuration Register

0x18 - RCC Domain 1 Clock Configuration Register

0x1c - RCC Domain 2 Clock Configuration Register

0x20 - RCC Domain 3 Clock Configuration Register

0x28 - RCC PLLs Clock Source Selection Register

0x2c - RCC PLLs Configuration Register

0x30 - RCC PLL1 Dividers Configuration Register

0x34 - RCC PLL1 Fractional Divider Register

0x38 - RCC PLL2 Dividers Configuration Register

0x3c - RCC PLL2 Fractional Divider Register

0x40 - RCC PLL3 Dividers Configuration Register

0x44 - RCC PLL3 Fractional Divider Register

0x4c - RCC Domain 1 Kernel Clock Configuration Register

0x50 - RCC Domain 2 Kernel Clock Configuration Register

0x54 - RCC Domain 2 Kernel Clock Configuration Register

0x58 - RCC Domain 3 Kernel Clock Configuration Register

0x60 - RCC Clock Source Interrupt Enable Register

0x64 - RCC Clock Source Interrupt Flag Register

0x68 - RCC Clock Source Interrupt Clear Register

0x70 - RCC Backup Domain Control Register

0x74 - RCC Clock Control and Status Register

0x7c - RCC AHB3 Reset Register

0x80 - RCC AHB1 Peripheral Reset Register

0x84 - RCC AHB2 Peripheral Reset Register

0x88 - RCC AHB4 Peripheral Reset Register

0x8c - RCC APB3 Peripheral Reset Register

0x90 - RCC APB1 Peripheral Reset Register

0x94 - RCC APB1 Peripheral Reset Register

0x98 - RCC APB2 Peripheral Reset Register

0x9c - RCC APB4 Peripheral Reset Register

0xa0 - RCC Global Control Register

0xa8 - RCC D3 Autonomous mode Register

0xd0 - RCC Reset Status Register

0xd4 - RCC AHB3 Clock Register

0xd8 - RCC AHB1 Clock Register

0xdc - RCC AHB2 Clock Register

0xe0 - RCC AHB4 Clock Register

0xe4 - RCC APB3 Clock Register

0xe8 - RCC APB1 Clock Register

0xec - RCC APB1 Clock Register

0xf0 - RCC APB2 Clock Register

0xf4 - RCC APB4 Clock Register

0xfc - RCC AHB3 Sleep Clock Register

0x100 - RCC AHB1 Sleep Clock Register

0x104 - RCC AHB2 Sleep Clock Register

0x108 - RCC AHB4 Sleep Clock Register

0x10c - RCC APB3 Sleep Clock Register

0x110 - RCC APB1 Low Sleep Clock Register

0x114 - RCC APB1 High Sleep Clock Register

0x118 - RCC APB2 Sleep Clock Register

0x11c - RCC APB4 Sleep Clock Register

0x130 - RCC Reset Status Register

0x134 - RCC AHB3 Clock Register

0x138 - RCC AHB1 Clock Register

0x13c - RCC AHB2 Clock Register

0x140 - RCC AHB4 Clock Register

0x144 - RCC APB3 Clock Register

0x148 - RCC APB1 Clock Register

0x14c - RCC APB1 Clock Register

0x150 - RCC APB2 Clock Register

0x154 - RCC APB4 Clock Register

0x15c - RCC AHB3 Sleep Clock Register

0x160 - RCC AHB1 Sleep Clock Register

0x164 - RCC AHB2 Sleep Clock Register

0x168 - RCC AHB4 Sleep Clock Register

0x16c - RCC APB3 Sleep Clock Register

0x170 - RCC APB1 Low Sleep Clock Register

0x174 - RCC APB1 High Sleep Clock Register

0x178 - RCC APB2 Sleep Clock Register

0x17c - RCC APB4 Sleep Clock Register

Trait Implementations

Auto Trait Implementations

impl Send for RegisterBlock

impl !Sync for RegisterBlock