Struct stm32h743::fdcan1::fdcan_ttir::W
[−]
[src]
pub struct W { /* fields omitted */ }Value to write to the register
Methods
impl W[src]
pub fn reset_value() -> W[src]
Reset value of the register
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self[src]
Writes raw bits to the register
pub fn sbc(&mut self) -> _SBCW[src]
Bit 0 - Start of Basic Cycle
pub fn smc(&mut self) -> _SMCW[src]
Bit 1 - Start of Matrix Cycle
pub fn csm(&mut self) -> _CSMW[src]
Bit 2 - Change of Synchronization Mode
pub fn sog(&mut self) -> _SOGW[src]
Bit 3 - Start of Gap
pub fn rtmi(&mut self) -> _RTMIW[src]
Bit 4 - Register Time Mark Interrupt.
pub fn ttmi(&mut self) -> _TTMIW[src]
Bit 5 - Trigger Time Mark Event Internal
pub fn swe(&mut self) -> _SWEW[src]
Bit 6 - Stop Watch Event
pub fn gtw(&mut self) -> _GTWW[src]
Bit 7 - Global Time Wrap
pub fn gtd(&mut self) -> _GTDW[src]
Bit 8 - Global Time Discontinuity
pub fn gte(&mut self) -> _GTEW[src]
Bit 9 - Global Time Error
pub fn txu(&mut self) -> _TXUW[src]
Bit 10 - Tx Count Underflow
pub fn txo(&mut self) -> _TXOW[src]
Bit 11 - Tx Count Overflow
pub fn se1(&mut self) -> _SE1W[src]
Bit 12 - Scheduling Error 1
pub fn se2(&mut self) -> _SE2W[src]
Bit 13 - Scheduling Error 2
pub fn elc(&mut self) -> _ELCW[src]
Bit 14 - Error Level Changed.
pub fn iwtg(&mut self) -> _IWTGW[src]
Bit 15 - Initialization Watch Trigger
pub fn wt(&mut self) -> _WTW[src]
Bit 16 - Watch Trigger
pub fn aw(&mut self) -> _AWW[src]
Bit 17 - Application Watchdog
pub fn cer(&mut self) -> _CERW[src]
Bit 18 - Configuration Error