Struct stm32h743::fdcan1::fdcan_ttils::R
[−]
[src]
pub struct R { /* fields omitted */ }Value read from the register
Methods
impl R[src]
pub fn bits(&self) -> u32[src]
Value of the register as raw bits
pub fn sbcl(&self) -> SBCLR[src]
Bit 0 - Start of Basic Cycle Interrupt Line
pub fn smcl(&self) -> SMCLR[src]
Bit 1 - Start of Matrix Cycle Interrupt Line
pub fn csml(&self) -> CSMLR[src]
Bit 2 - Change of Synchronization Mode Interrupt Line
pub fn sogl(&self) -> SOGLR[src]
Bit 3 - Start of Gap Interrupt Line
pub fn rtmil(&self) -> RTMILR[src]
Bit 4 - Register Time Mark Interrupt Line
pub fn ttmil(&self) -> TTMILR[src]
Bit 5 - Trigger Time Mark Event Internal Interrupt Line
pub fn swel(&self) -> SWELR[src]
Bit 6 - Stop Watch Event Interrupt Line
pub fn gtwl(&self) -> GTWLR[src]
Bit 7 - Global Time Wrap Interrupt Line
pub fn gtdl(&self) -> GTDLR[src]
Bit 8 - Global Time Discontinuity Interrupt Line
pub fn gtel(&self) -> GTELR[src]
Bit 9 - Global Time Error Interrupt Line
pub fn txul(&self) -> TXULR[src]
Bit 10 - Tx Count Underflow Interrupt Line
pub fn txol(&self) -> TXOLR[src]
Bit 11 - Tx Count Overflow Interrupt Line
pub fn se1l(&self) -> SE1LR[src]
Bit 12 - Scheduling Error 1 Interrupt Line
pub fn se2l(&self) -> SE2LR[src]
Bit 13 - Scheduling Error 2 Interrupt Line
pub fn elcl(&self) -> ELCLR[src]
Bit 14 - Change Error Level Interrupt Line
pub fn iwtgl(&self) -> IWTGLR[src]
Bit 15 - Initialization Watch Trigger Interrupt Line
pub fn wtl(&self) -> WTLR[src]
Bit 16 - Watch Trigger Interrupt Line
pub fn awl(&self) -> AWLR[src]
Bit 17 - Application Watchdog Interrupt Line
pub fn cerl(&self) -> CERLR[src]
Bit 18 - Configuration Error Interrupt Line