Struct stm32h743::fdcan1::fdcan_ttir::R
[−]
[src]
pub struct R { /* fields omitted */ }Value read from the register
Methods
impl R[src]
pub fn bits(&self) -> u32[src]
Value of the register as raw bits
pub fn sbc(&self) -> SBCR[src]
Bit 0 - Start of Basic Cycle
pub fn smc(&self) -> SMCR[src]
Bit 1 - Start of Matrix Cycle
pub fn csm(&self) -> CSMR[src]
Bit 2 - Change of Synchronization Mode
pub fn sog(&self) -> SOGR[src]
Bit 3 - Start of Gap
pub fn rtmi(&self) -> RTMIR[src]
Bit 4 - Register Time Mark Interrupt.
pub fn ttmi(&self) -> TTMIR[src]
Bit 5 - Trigger Time Mark Event Internal
pub fn swe(&self) -> SWER[src]
Bit 6 - Stop Watch Event
pub fn gtw(&self) -> GTWR[src]
Bit 7 - Global Time Wrap
pub fn gtd(&self) -> GTDR[src]
Bit 8 - Global Time Discontinuity
pub fn gte(&self) -> GTER[src]
Bit 9 - Global Time Error
pub fn txu(&self) -> TXUR[src]
Bit 10 - Tx Count Underflow
pub fn txo(&self) -> TXOR[src]
Bit 11 - Tx Count Overflow
pub fn se1(&self) -> SE1R[src]
Bit 12 - Scheduling Error 1
pub fn se2(&self) -> SE2R[src]
Bit 13 - Scheduling Error 2
pub fn elc(&self) -> ELCR[src]
Bit 14 - Error Level Changed.
pub fn iwtg(&self) -> IWTGR[src]
Bit 15 - Initialization Watch Trigger
pub fn wt(&self) -> WTR[src]
Bit 16 - Watch Trigger
pub fn aw(&self) -> AWR[src]
Bit 17 - Application Watchdog
pub fn cer(&self) -> CERR[src]
Bit 18 - Configuration Error