Struct stm32h7::stm32h747cm7::sdmmc1::maskr::R

pub struct R(_);

Register MASKR reader

Implementations

impl R

pub fn ccrcfailie(&self) -> CCRCFAILIE_R

Bit 0 - Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure.

pub fn dcrcfailie(&self) -> DCRCFAILIE_R

Bit 1 - Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure.

pub fn ctimeoutie(&self) -> CTIMEOUTIE_R

Bit 2 - Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout.

pub fn dtimeoutie(&self) -> DTIMEOUTIE_R

Bit 3 - Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout.

pub fn txunderrie(&self) -> TXUNDERRIE_R

Bit 4 - Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error.

pub fn rxoverrie(&self) -> RXOVERRIE_R

Bit 5 - Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error.

pub fn cmdrendie(&self) -> CMDRENDIE_R

Bit 6 - Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response.

pub fn cmdsentie(&self) -> CMDSENTIE_R

Bit 7 - Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command.

pub fn dataendie(&self) -> DATAENDIE_R

Bit 8 - Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end.

pub fn dholdie(&self) -> DHOLDIE_R

Bit 9 - Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state.

pub fn dbckendie(&self) -> DBCKENDIE_R

Bit 10 - Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end.

pub fn dabortie(&self) -> DABORTIE_R

Bit 11 - Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted.

pub fn txfifoheie(&self) -> TXFIFOHEIE_R

Bit 14 - Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty.

pub fn rxfifohfie(&self) -> RXFIFOHFIE_R

Bit 15 - Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full.

pub fn rxfifofie(&self) -> RXFIFOFIE_R

Bit 17 - Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full.

pub fn txfifoeie(&self) -> TXFIFOEIE_R

Bit 18 - Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty.

pub fn busyd0endie(&self) -> BUSYD0ENDIE_R

Bit 21 - BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response.

pub fn sdioitie(&self) -> SDIOITIE_R

Bit 22 - SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt.

pub fn ackfailie(&self) -> ACKFAILIE_R

Bit 23 - Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail.

pub fn acktimeoutie(&self) -> ACKTIMEOUTIE_R

Bit 24 - Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout.

pub fn vswendie(&self) -> VSWENDIE_R

Bit 25 - Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion.

pub fn ckstopie(&self) -> CKSTOPIE_R

Bit 26 - Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped.

pub fn idmabtcie(&self) -> IDMABTCIE_R

Bit 28 - IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer.

Methods from Deref<Target = R<MASKR_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<MASKR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<MASKR_SPEC>> for R

fn from(reader: R<MASKR_SPEC>) -> Self

Converts to this type from the input type.