Struct stm32h7::stm32h743v::sai4::ch::cr1::W

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pub struct W(_);

Expand description

Register CR1 writer

Implementations

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impl W

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pub fn mode(&mut self) -> MODE_W<'_, 0>

Bits 0:1 - SAIx audio block mode immediately

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pub fn prtcfg(&mut self) -> PRTCFG_W<'_, 2>

Bits 2:3 - Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled.

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pub fn ds(&mut self) -> DS_W<'_, 5>

Bits 5:7 - Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled.

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pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_, 8>

Bit 8 - Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first.

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pub fn ckstr(&mut self) -> CKSTR_W<'_, 9>

Bit 9 - Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol.

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pub fn syncen(&mut self) -> SYNCEN_W<'_, 10>

Bits 10:11 - Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled.

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pub fn mono(&mut self) -> MONO_W<'_, 12>

Bit 12 - Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details.

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pub fn outdriv(&mut self) -> OUTDRIV_W<'_, 13>

Bit 13 - Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration.

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pub fn saien(&mut self) -> SAIEN_W<'_, 16>

Bit 16 - Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit.

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pub fn dmaen(&mut self) -> DMAEN_W<'_, 17>

Bit 17 - DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode.

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pub fn mckdiv(&mut self) -> MCKDIV_W<'_, 20>

Bits 20:25 - Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:

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