pub struct W(_);
Expand description

Register SDCR writer

Implementations

Bits 0:1 - Number of column address bits These bits define the number of bits of a column address.

Bits 2:3 - Number of row address bits These bits define the number of bits of a row address.

Bits 4:5 - Memory data bus width. These bits define the memory device width.

Bit 6 - Number of internal banks This bit sets the number of internal banks.

Bits 7:8 - CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles

Bit 9 - Write protection This bit enables write mode access to the SDRAM bank.

Bits 10:11 - SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register is read only.

Bit 12 - Burst read This bit enables burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read only.

Bits 13:14 - Read pipe These bits define the delay, in KCK_FMC clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only.

Writes raw bits to the register.

Methods from Deref<Target = W<SDCR_SPEC>>

Writes raw bits to the register.

Trait Implementations

The resulting type after dereferencing.

Dereferences the value.

Mutably dereferences the value.

Converts to this type from the input type.

Auto Trait Implementations

Blanket Implementations

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Immutably borrows from an owned value. Read more

Mutably borrows from an owned value. Read more

Returns the argument unchanged.

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

The type returned in the event of a conversion error.

Performs the conversion.

The type returned in the event of a conversion error.

Performs the conversion.