Struct stm32h7::stm32h743v::rcc::pllcfgr::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn pll1fracen(&self) -> PLL1FRACENR

Bit 0 - PLL1 fractional latch enable

pub fn pll1vcosel(&self) -> PLL1VCOSELR

Bit 1 - PLL1 VCO selection

pub fn pll1rge(&self) -> PLL1RGER

Bits 2:3 - PLL1 input frequency range

pub fn pll2fracen(&self) -> PLL2FRACENR

Bit 4 - PLL2 fractional latch enable

pub fn pll2vcosel(&self) -> PLL2VCOSELR

Bit 5 - PLL2 VCO selection

pub fn pll2rge(&self) -> PLL2RGER

Bits 6:7 - PLL2 input frequency range

pub fn pll3fracen(&self) -> PLL3FRACENR

Bit 8 - PLL3 fractional latch enable

pub fn pll3vcosel(&self) -> PLL3VCOSELR

Bit 9 - PLL3 VCO selection

pub fn pll3rge(&self) -> PLL3RGER

Bits 10:11 - PLL3 input frequency range

pub fn divp1en(&self) -> DIVP1ENR

Bit 16 - PLL1 DIVP divider output enable

pub fn divq1en(&self) -> DIVQ1ENR

Bit 17 - PLL1 DIVQ divider output enable

pub fn divr1en(&self) -> DIVR1ENR

Bit 18 - PLL1 DIVR divider output enable

pub fn divp2en(&self) -> DIVP2ENR

Bit 19 - PLL2 DIVP divider output enable

pub fn divq2en(&self) -> DIVQ2ENR

Bit 20 - PLL2 DIVQ divider output enable

pub fn divr2en(&self) -> DIVR2ENR

Bit 21 - PLL2 DIVR divider output enable

pub fn divp3en(&self) -> DIVP3ENR

Bit 22 - PLL3 DIVP divider output enable

pub fn divq3en(&self) -> DIVQ3ENR

Bit 23 - PLL3 DIVQ divider output enable

pub fn divr3en(&self) -> DIVR3ENR

Bit 24 - PLL3 DIVR divider output enable