Struct stm32h7::stm32h743v::fmc::sdcr1::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn nc(&mut self) -> _NCW

Bits 0:1 - Number of column address bits These bits define the number of bits of a column address.

pub fn nr(&mut self) -> _NRW

Bits 2:3 - Number of row address bits These bits define the number of bits of a row address.

pub fn mwid(&mut self) -> _MWIDW

Bits 4:5 - Memory data bus width. These bits define the memory device width.

pub fn nb(&mut self) -> _NBW

Bit 6 - Number of internal banks This bit sets the number of internal banks.

pub fn cas(&mut self) -> _CASW

Bits 7:8 - CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles

pub fn wp(&mut self) -> _WPW

Bit 9 - Write protection This bit enables write mode access to the SDRAM bank.

pub fn sdclk(&mut self) -> _SDCLKW

Bits 10:11 - SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register is read only.

pub fn rburst(&mut self) -> _RBURSTW

Bit 12 - Burst read This bit enables burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read only.

pub fn rpipe(&mut self) -> _RPIPEW

Bits 13:14 - Read pipe These bits define the delay, in KCK_FMC clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only.