Struct stm32h7::stm32h743::sdmmc1::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub power: POWER,
    pub clkcr: CLKCR,
    pub argr: ARGR,
    pub cmdr: CMDR,
    pub respcmdr: RESPCMDR,
    pub resp1r: RESP1R,
    pub resp2r: RESP2R,
    pub resp3r: RESP3R,
    pub resp4r: RESP4R,
    pub dtimer: DTIMER,
    pub dlenr: DLENR,
    pub dctrl: DCTRL,
    pub dcntr: DCNTR,
    pub star: STAR,
    pub icr: ICR,
    pub maskr: MASKR,
    pub acktimer: ACKTIMER,
    pub idmactrlr: IDMACTRLR,
    pub idmabsizer: IDMABSIZER,
    pub idmabase0r: IDMABASE0R,
    pub idmabase1r: IDMABASE1R,
    pub fifor: FIFOR,
    pub ver: VER,
    pub id: ID,
    // some fields omitted
}

Register block

Fields

power: POWER

0x00 - SDMMC power control register

clkcr: CLKCR

0x04 - The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width.

argr: ARGR

0x08 - The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.

cmdr: CMDR

0x0c - The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).

respcmdr: RESPCMDR

0x10 - SDMMC command response register

resp1r: RESP1R

0x14 - The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

resp2r: RESP2R

0x18 - The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

resp3r: RESP3R

0x1c - The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

resp4r: RESP4R

0x20 - The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

dtimer: DTIMER

0x24 - The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.

dlenr: DLENR

0x28 - The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.

dctrl: DCTRL

0x2c - The SDMMC_DCTRL register control the data path state machine (DPSM).

dcntr: DCNTR

0x30 - The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.

star: STAR

0x34 - The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)

icr: ICR

0x38 - The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.

maskr: MASKR

0x3c - The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.

acktimer: ACKTIMER

0x40 - The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.

idmactrlr: IDMACTRLR

0x50 - The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.

idmabsizer: IDMABSIZER

0x54 - The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration.

idmabase0r: IDMABASE0R

0x58 - The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration.

idmabase1r: IDMABASE1R

0x5c - The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address.

fifor: FIFOR

0x80 - The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

ver: VER

0x3f4 - SDMMC IP version register

id: ID

0x3f8 - SDMMC IP identification register