Struct stm32h7::stm32h743::sdmmc1::star::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn ccrcfail(&self) -> CCRCFAILR

Bit 0 - Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn dcrcfail(&self) -> DCRCFAILR

Bit 1 - Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn ctimeout(&self) -> CTIMEOUTR

Bit 2 - Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods.

pub fn dtimeout(&self) -> DTIMEOUTR

Bit 3 - Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn txunderr(&self) -> TXUNDERRR

Bit 4 - Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn rxoverr(&self) -> RXOVERRR

Bit 5 - Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn cmdrend(&self) -> CMDRENDR

Bit 6 - Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn cmdsent(&self) -> CMDSENTR

Bit 7 - Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn dataend(&self) -> DATAENDR

Bit 8 - Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn dhold(&self) -> DHOLDR

Bit 9 - Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn dbckend(&self) -> DBCKENDR

Bit 10 - Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn dabort(&self) -> DABORTR

Bit 11 - Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn dpsmact(&self) -> DPSMACTR

Bit 12 - Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt.

pub fn cpsmact(&self) -> CPSMACTR

Bit 13 - Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt.

pub fn txfifohe(&self) -> TXFIFOHER

Bit 14 - Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full.

pub fn rxfifohf(&self) -> RXFIFOHFR

Bit 15 - Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty.

pub fn txfifof(&self) -> TXFIFOFR

Bit 16 - Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty.

pub fn rxfifof(&self) -> RXFIFOFR

Bit 17 - Receive FIFO full This bit is cleared when one FIFO location becomes empty.

pub fn txfifoe(&self) -> TXFIFOER

Bit 18 - Transmit FIFO empty This bit is cleared when one FIFO location becomes full.

pub fn rxfifoe(&self) -> RXFIFOER

Bit 19 - Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full.

pub fn busyd0(&self) -> BUSYD0R

Bit 20 - Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt.

pub fn busyd0end(&self) -> BUSYD0ENDR

Bit 21 - end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn sdioit(&self) -> SDIOITR

Bit 22 - SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn ackfail(&self) -> ACKFAILR

Bit 23 - Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn acktimeout(&self) -> ACKTIMEOUTR

Bit 24 - Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn vswend(&self) -> VSWENDR

Bit 25 - Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn ckstop(&self) -> CKSTOPR

Bit 26 - SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn idmate(&self) -> IDMATER

Bit 27 - IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.

pub fn idmabtc(&self) -> IDMABTCR

Bit 28 - IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.