Struct stm32h7::stm32h743::mdma::c7isr::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn teif7(&self) -> TEIF7R

Bit 0 - Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.

pub fn ctcif7(&self) -> CTCIF7R

Bit 1 - Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.

pub fn brtif7(&self) -> BRTIF7R

Bit 2 - Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.

pub fn btif7(&self) -> BTIF7R

Bit 3 - Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.

pub fn tcif7(&self) -> TCIF7R

Bit 4 - channel x buffer transfer complete

pub fn crqa7(&self) -> CRQA7R

Bit 16 - channel x request active flag