Struct stm32h7::stm32h743::mdma::c4cr::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn en(&mut self) -> _ENW

Bit 0 - channel enable

pub fn teie(&mut self) -> _TEIEW

Bit 1 - Transfer error interrupt enable This bit is set and cleared by software.

pub fn ctcie(&mut self) -> _CTCIEW

Bit 2 - Channel Transfer Complete interrupt enable This bit is set and cleared by software.

pub fn brtie(&mut self) -> _BRTIEW

Bit 3 - Block Repeat transfer interrupt enable This bit is set and cleared by software.

pub fn btie(&mut self) -> _BTIEW

Bit 4 - Block Transfer interrupt enable This bit is set and cleared by software.

pub fn tcie(&mut self) -> _TCIEW

Bit 5 - buffer Transfer Complete interrupt enable This bit is set and cleared by software.

pub fn pl(&mut self) -> _PLW

Bits 6:7 - Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.

pub fn bex(&mut self) -> _BEXW

Bit 12 - byte Endianness exchange

pub fn hex(&mut self) -> _HEXW

Bit 13 - Half word Endianes exchange

pub fn wex(&mut self) -> _WEXW

Bit 14 - Word Endianness exchange

pub fn swrq(&mut self) -> _SWRQW

Bit 16 - SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).