Struct stm32h7::stm32h743v::fmc::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub bcr1: BCR1,
    pub btr1: BTR1,
    pub bcr2: BCR2,
    pub btr2: BTR2,
    pub bcr3: BCR3,
    pub btr3: BTR3,
    pub bcr4: BCR4,
    pub btr4: BTR4,
    pub pcr: PCR,
    pub sr: SR,
    pub pmem: PMEM,
    pub patt: PATT,
    pub eccr: ECCR,
    pub bwtr1: BWTR1,
    pub bwtr2: BWTR2,
    pub bwtr3: BWTR3,
    pub bwtr4: BWTR4,
    pub sdcr1: SDCR1,
    pub sdcr2: SDCR2,
    pub sdtr1: SDTR1,
    pub sdtr2: SDTR2,
    pub sdcmr: SDCMR,
    pub sdrtr: SDRTR,
    pub sdsr: SDSR,
    // some fields omitted
}

Register block

Fields

bcr1: BCR1

0x00 - This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.

btr1: BTR1

0x04 - This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

bcr2: BCR2

0x08 - This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.

btr2: BTR2

0x0c - This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

bcr3: BCR3

0x10 - This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.

btr3: BTR3

0x14 - This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

bcr4: BCR4

0x18 - This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.

btr4: BTR4

0x1c - This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

pcr: PCR

0x80 - NAND Flash control registers

sr: SR

0x84 - This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.

pmem: PMEM

0x88 - The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.

patt: PATT

0x8c - The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).

eccr: ECCR

0x94 - This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.

bwtr1: BWTR1

0x104 - This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

bwtr2: BWTR2

0x10c - This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

bwtr3: BWTR3

0x114 - This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

bwtr4: BWTR4

0x11c - This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

sdcr1: SDCR1

0x140 - This register contains the control parameters for each SDRAM memory bank

sdcr2: SDCR2

0x144 - This register contains the control parameters for each SDRAM memory bank

sdtr1: SDTR1

0x148 - This register contains the timing parameters of each SDRAM bank

sdtr2: SDTR2

0x14c - This register contains the timing parameters of each SDRAM bank

sdcmr: SDCMR

0x150 - This register contains the command issued when the SDRAM device is accessed. This register is used to initialize the SDRAM device, and to activate the Self-refresh and the Power-down modes. As soon as the MODE field is written, the command will be issued only to one or to both SDRAM banks according to CTB1 and CTB2 command bits. This register is the same for both SDRAM banks.

sdrtr: SDRTR

0x154 - This register sets the refresh rate in number of SDCLK clock cycles between the refresh cycles by configuring the Refresh Timer Count value.Examplewhere 64 ms is the SDRAM refresh period.The refresh rate must be increased by 20 SDRAM clock cycles (as in the above example) to obtain a safe margin if an internal refresh request occurs when a read request has been accepted. It corresponds to a COUNT value of 0000111000000 (448). This 13-bit field is loaded into a timer which is decremented using the SDRAM clock. This timer generates a refresh pulse when zero is reached. The COUNT value must be set at least to 41 SDRAM clock cycles.As soon as the FMC_SDRTR register is programmed, the timer starts counting. If the value programmed in the register is 0, no refresh is carried out. This register must not be reprogrammed after the initialization procedure to avoid modifying the refresh rate.Each time a refresh pulse is generated, this 13-bit COUNT field is reloaded into the counter.If a memory access is in progress, the Auto-refresh request is delayed. However, if the memory access and Auto-refresh requests are generated simultaneously, the Auto-refresh takes precedence. If the memory access occurs during a refresh operation, the request is buffered to be processed when the refresh is complete.This register is common to SDRAM bank 1 and bank 2.

sdsr: SDSR

0x158 - SDRAM Status register